Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7003639 | Memory controller with power management logic | Ely Tsern, Richard M. Barth, Steven C. Woo | 2006-02-21 |
| 6782460 | Pipelined memory controller and method of controlling access to memory devices in a memory system | Richard M. Barth | 2004-08-24 |
| 6754783 | Memory controller with power management logic | Ely Tsern, Richard M. Barth, Steven C. Woo | 2004-06-22 |
| 6640292 | System and method for controlling retire buffer operation in a memory system | Richard M. Barth, Anil V. Godbole | 2003-10-28 |
| 6571325 | Pipelined memory controller and method of controlling access to memory devices in a memory system | Richard M. Barth | 2003-05-27 |
| 6523089 | Memory controller with power management logic | Ely Tsern, Richard M. Barth, Steven C. Woo | 2003-02-18 |
| 6453401 | Memory controller with timing constraint tracking and checking unit and corresponding method | Richard M. Barth, Anil V. Godbole | 2002-09-17 |
| 6373768 | Apparatus and method for thermal regulation in memory subsystems | Steven C. Woo, Richard M. Barth, Ely Tsern, Craig E. Hampel | 2002-04-16 |
| 6310814 | Rambus DRAM (RDRAM) apparatus and method for performing refresh operations | Craig E. Hampel, Richard M. Barth, Paul G. Davis, Bradley A. May, Frederick A. Ware | 2001-10-30 |
| 6195733 | Method to share memory in a single chip multiprocessor system | N. Gopalan Nair, David Regenold, Parviz Hatami | 2001-02-27 |
| 6021076 | Apparatus and method for thermal regulation in memory subsystems | Steven C. Woo, Richard M. Barth, Ely Tsern, Craig E. Hampel | 2000-02-01 |
| 5909702 | Memory address translations for programs code execution/relocation | Marc Jalfon, David Regenold, Franco Ricci | 1999-06-01 |
| 5890013 | Paged memory architecture for a single chip multi-processor with physical memory pages that are swapped without latency | N. Gopalan Nair, David Regenold, Parviz Hatami | 1999-03-30 |
| 5513346 | Error condition detector for handling interrupt in integrated circuits having multiple processors | David Regenold | 1996-04-30 |