Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7685379 | Cache memory to support a processor's power mode of operation | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Steven Tu | 2010-03-23 |
| 7640387 | Method and apparatus for implementing heterogeneous interconnects | Samantha J. Edirisooriya, Steven Tu, Gregory Tse, Sujat Jamil, David E. Miner +1 more | 2009-12-29 |
| 7634603 | System and apparatus for early fixed latency subtractive decoding | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Steven Tu, Hang T. Nguyen | 2009-12-15 |
| 7487299 | Cache memory to support a processor's power mode of operation | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Steven Tu | 2009-02-03 |
| 7464227 | Method and apparatus for supporting opportunistic sharing in coherent multiprocessors | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Steven Tu, Hang T. Nguyen | 2008-12-09 |
| 7428607 | Apparatus and method for arbitrating heterogeneous agents in on-chip busses | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Steven Tu, Hang T. Nguyen | 2008-09-23 |
| 7406552 | Systems and methods for early fixed latency subtractive decoding including speculative acknowledging | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Steven Tu, Hang T. Nguyen | 2008-07-29 |
| 7406553 | System and apparatus for early fixed latency subtractive decoding | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Steven Tu, Hang T. Nguyen | 2008-07-29 |
| 7404043 | Cache memory to support a processor's power mode of operation | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Steven Tu | 2008-07-22 |
| 7366845 | Pushing of clean data to one or more processors in a system having a coherency protocol | Sujat Jamil, Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, Steven Tu | 2008-04-29 |
| 7353317 | Method and apparatus for implementing heterogeneous interconnects | Samantha J. Edirisooriya, Steven Tu, Gregory Tse, Sujat Jamil, David E. Miner +1 more | 2008-04-01 |
| 7290093 | Cache memory to support a processor's power mode of operation | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Steven Tu | 2007-10-30 |
| 7234028 | Power/performance optimized cache using memory write prevention through write snarfing | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Steven Tu | 2007-06-19 |
| 7219176 | System and apparatus for early fixed latency subtractive decoding | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Steven Tu, Hang T. Nguyen | 2007-05-15 |
| 7159077 | Direct processor cache access within a system having a coherent multi-processor protocol | Steven Tu, Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Hang T. Nguyen | 2007-01-02 |
| 7143220 | Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Steven Tu, Hang T. Nguyen | 2006-11-28 |
| 7100001 | Methods and apparatus for cache intervention | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Steven Tu, Mark Fullerton +1 more | 2006-08-29 |
| 7062613 | Methods and apparatus for cache intervention | Sujat Jamil, Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, Steven Tu | 2006-06-13 |
| 6983348 | Methods and apparatus for cache intervention | Sujat Jamil, Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, Steven Tu | 2006-01-03 |
| 6775748 | Methods and apparatus for transferring cache block ownership | Sujat Jamil, Samantha J. Edirisooriya, David E. Miner, Steven Tu | 2004-08-10 |
| RE38045 | Data compensation/resynchronization circuit for phase lock loops | Aldo Giovanni Cometti | 2003-03-25 |
| 5777498 | Data compensation/resynchronization circuit for phase lock loops | Aldo Giovanni Cometti | 1998-07-07 |