Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6148321 | Processor event recognition | — | 2000-11-14 |
| 6128706 | Apparatus and method for a load bias--load with intent to semaphore | William R. Bryg, Stephen G. Burger, Michael L. Ziegler | 2000-10-03 |
| 6088780 | Page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address | Koichi Yamada, Jim Hays, Jonathan Ross, Stephen G. Burger, William R. Bryg | 2000-07-11 |
| 6065115 | Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction | Harshvardhan Sharangpani, Hans Mulder, Judge K. Arora | 2000-05-16 |
| 6065105 | Dependency matrix | Nazar Zaidi, Ken Shoemaker, Jeff Baxter | 2000-05-16 |
| 6055652 | Multiple segment register use with different operand size | Nazar Zaidi, Kenneth D. Shoemaker | 2000-04-25 |
| 6052801 | Method and apparatus for providing breakpoints on a selectable address range | Donald B. Alpert | 2000-04-18 |
| 6049897 | Multiple segment register use with different operand size | Nazar Zaidi, Kenneth D. Shoemaker | 2000-04-11 |
| 6049864 | Method for scheduling a flag generating instruction and a subsequent instruction by executing the flag generating instruction in a microprocessor | Kin-Yip Liu, Ken Shoemaker, Anand Pai, Krishna M. Yellamilli | 2000-04-11 |
| 6016540 | Method and apparatus for scheduling instructions in waves | Nazar Zaidi, Ken Shoemaker | 2000-01-18 |
| 6012132 | Method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table | Koichi Yamada | 2000-01-04 |
| 6006325 | Method and apparatus for instruction and data serialization in a computer processor | Stephen G. Burger, William R. Bryg | 1999-12-21 |
| 5978900 | Renaming numeric and segment registers using common general register pool | Kin-Yip Liu, Kenneth D. Shoemaker, Anand Pai | 1999-11-02 |
| 5940872 | Software and hardware-managed translation lookaside buffer | Koichi Yamada, Stephen G. Burger, James O. Hays, Jonathan Ross, William R. Bryg | 1999-08-17 |
| 5918250 | Method and apparatus for preloading default address translation attributes | — | 1999-06-29 |
| 5918251 | Method and apparatus for preloading different default address translation attributes | Koichi Yamada | 1999-06-29 |
| 5915117 | Computer architecture for the deferral of exceptions on speculative instructions | Jonathan Ross, Jack Mills, James O. Hays, Stephen G. Burger, Dale Morris +4 more | 1999-06-22 |
| 5895489 | Memory management system including an inclusion bit for maintaining cache coherency | Pradeep Kumar Dubey, Mustafiz R. Choudhury | 1999-04-20 |
| 5860017 | Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction | Harshvardhan Sharangpani, Hans Mulder, Judge K. Arora | 1999-01-12 |
| 5832260 | Processor microarchitecture for efficient processing of instructions in a program including a conditional program flow control instruction | Judge K. Arora, Harshvardhan Sharangpani | 1998-11-03 |
| 5809563 | Method and apparatus utilizing a region based page table walk bit | Koichi Yamada | 1998-09-15 |
| 5774686 | Method and apparatus for providing two system architectures in a processor | Donald B. Alpert, Kevin C. Kahn, Harsh Sharangpani | 1998-06-30 |
| 5752275 | Translation look-aside buffer including a single page size translation unit | — | 1998-05-12 |
| 5740413 | Method and apparatus for providing address breakpoints, branch breakpoints, and single stepping | Donald B. Alpert | 1998-04-14 |
| 5659679 | Method and apparatus for providing breakpoints on taken jumps and for providing software profiling in a computer system | Donald B. Alpert | 1997-08-19 |