KY

Krishna M. Yellamilli

IN Intel: 3 patents #10,349 of 30,777Top 35%
📍 San Jose, CA: #14,517 of 32,062 inventorsTop 50%
🗺 California: #149,087 of 386,348 inventorsTop 40%
Overall (All Time): #1,627,573 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
6049864 Method for scheduling a flag generating instruction and a subsequent instruction by executing the flag generating instruction in a microprocessor Kin-Yip Liu, Ken Shoemaker, Gary N. Hammond, Anand Pai 2000-04-11
5189319 Power reducing buffer/latch circuit Wingcho Fung 1993-02-23
5148052 Recirculating transparent latch employing a multiplexing circuit 1992-09-15