Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6799268 | Branch ordering buffer | Shlomit Weiss, Alan B. Kyker | 2004-09-28 |
| 6779103 | Control word register renaming | William C. Alexander, Mehul Dave | 2004-08-17 |
| 6735688 | Processor having replay architecture with fast and slow replay paths | Michael D. Upton, David J. Sager, Glenn J. Hinton | 2004-05-11 |
| 6665792 | Interface to a memory system for a processor having a replay system | Amit Merchant, David J. Sager | 2003-12-16 |
| 6651158 | Determination of approaching instruction starvation of threads based on a plurality of conditions | David William Burns, James D. Allen, IV, Michael D. Upton, Alan B. Kyker | 2003-11-18 |
| 6633970 | Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer | David W. Clift, David J. Sager | 2003-10-14 |
| 6591344 | Method and system for an INUSE field resource management scheme | Alan B. Kyker | 2003-07-08 |
| 6496925 | Method and apparatus for processing an event occurrence within a multithreaded processor | Dion Rodgers, Amit Merchant, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur | 2002-12-17 |
| 6467027 | Method and system for an INUSE field resource management scheme | Alan B. Kyker | 2002-10-15 |
| 6457119 | Processor instruction pipeline with error detection scheme | Robert F. Krick, Chan Woo Lee | 2002-09-24 |
| 6385715 | Multi-threading for a processor utilizing a replay queue | Amit Merchant, David J. Sager | 2002-05-07 |
| 6163838 | Computer processor with a replay system | Amit Merchant, David J. Sager | 2000-12-19 |
| 6094717 | Computer processor with a replay system having a plurality of checkers | Amit Merchant, David J. Sager, Michael D. Upton | 2000-07-25 |
| 6041403 | Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction | Donald D. Parker, Alan B. Kyker | 2000-03-21 |
| 6026477 | Branch recovery mechanism to reduce processor front end stall time by providing path information for both correct and incorrect instructions mixed in the instruction pool | Alan B. Kyker | 2000-02-15 |
| 5974523 | Mechanism for efficiently overlapping multiple operand types in a microprocessor | Andrew F. Glew, Michael A. Fetterman, Glenn J. Hinton, Robert P. Colwell, David B. Papworth | 1999-10-26 |
| 5913050 | Method and apparatus for providing address-size backward compatibility in a processor using segmented memory | Robert P. Colwell, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, David B. Papworth | 1999-06-15 |
| 5740393 | Instruction pointer limits in processor that performs speculative out-of-order instruction execution | Rohit A. Vidwans, Michael A. Fetterman, Andrew F. Glew | 1998-04-14 |
| 5687338 | Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor | Robert P. Colwell, Michael A. Fetterman, Andrew F. Glew, Ashwani K. Gupta, Glenn J. Hinton +1 more | 1997-11-11 |
| 5625788 | Microprocessor with novel instruction for signaling event occurrence and for providing event handling information in response thereto | Scott Dion Rodgers | 1997-04-29 |
| 5581717 | Decoding circuit and method providing immediate data for a micro-operation issued from a decoder | Gary L. Brown, Donald D. Parker | 1996-12-03 |
| 5566298 | Method for state recovery during assist and restart in a decoder having an alias mechanism | Gary L. Brown, Michael M. Hancock, Donald D. Parker, Gail M. Rupnick | 1996-10-15 |
| 5559974 | Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation | Gary L. Brown, Michael M. Hancock, Donald D. Parker | 1996-09-24 |
| 5537560 | Method and apparatus for conditionally generating a microinstruction that selects one of two values based upon control states of a microprocessor | Alan B. Kyker, Scott Dion Rodgers | 1996-07-16 |
| 5463745 | Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system | Rohit A. Vidwans, Michael A. Fetterman, Andrew F. Glew | 1995-10-31 |