Issued Patents All Time
Showing 26–50 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11042403 | Platform auto-configuration and tuning | Karl I. Taht, Ren Wang, James J. Greensky, Tsung-Yuan C. Tai | 2021-06-22 |
| 10860244 | Method and apparatus for multi-level memory early page demotion | Binh Pham, Alaa R. Alameldeen, Zeshan A. Chishti, Zhe Wang | 2020-12-08 |
| 10678692 | Method and system for coordinating baseline and secondary prefetchers | Seth H. Pugsley, Manjunath Shevgoor | 2020-06-09 |
| 10606755 | Method and system for performing data movement operations with read snapshot and in place write update | Anil Vasudevan, Venkata Krishnan, Andrew J. Herdrich, Ren Wang, Robert G. Blankenship +7 more | 2020-03-31 |
| 10528473 | Disabling cache portions during low voltage operations | Muhammad M. Khellah, Vivek K. De, Ming Zhang, Jaume Abella, Javier Carretero Casado +3 more | 2020-01-07 |
| 10521236 | Branch prediction based on coherence operations in processors | Binh Pham, Patrick Lu, Jared W. Stark, IV | 2019-12-31 |
| 10496544 | Aggregated write back in a direct mapped two level memory | Zhe Wang, Zeshan A. Chishti | 2019-12-03 |
| 10482017 | Processor, method, and system for cache partitioning and control for accurate performance monitoring and optimization | Karl I. Taht, Ren Wang, James J. Greensky | 2019-11-19 |
| 10452551 | Programmable memory prefetcher for prefetching multiple cache lines based on data in a prefetch engine control register | Ganesh Venkatesh, Seth H. Pugsley, Deborah T. Marr | 2019-10-22 |
| 10261901 | Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory | Zhe Wang, Zeshan A. Chishti, Seth H. Pugsley, Alaa R. Alameldeen, Shih-Lien Linus Lu | 2019-04-16 |
| 10229060 | Instruction and logic for software hints to improve hardware prefetcher effectiveness | Ren Wang, Namakkal N. Venkatesan, Patrick Lu | 2019-03-12 |
| 10210202 | Recognition of free-form gestures from orientation tracking of a handheld or wearable device | Nicolas G. Mitri, Mariette Awad | 2019-02-19 |
| 10120806 | Multi-level system memory with near memory scrubbing based on predicted far memory idle time | Zhe Wang, Zeshan A. Chishti | 2018-11-06 |
| 10108549 | Method and apparatus for pre-fetching data in a system having a multi-level system memory | Zhe Wang, Zeshan A. Chishti, Seth H. Pugsley, Alaa R. Alameldeen, Shih-Lien Linus Lu | 2018-10-23 |
| 10102134 | Instruction and logic for run-time evaluation of multiple prefetchers | Zeshan A. Chishti, Seth H. Pugsley, Peng-Fei Chuang, Robert L. Scott, Aamer Jaleel +2 more | 2018-10-16 |
| 10024916 | Sequential circuit with error detection | Keith Alan Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Shih-Lien Linus Lu +2 more | 2018-07-17 |
| 10019360 | Hardware predictor using a cache line demotion instruction to reduce performance inversion in core-to-core data transfers | Ren Wang, Andrew J. Herdrich | 2018-07-10 |
| 10007620 | System and method for cache replacement using conservative set dueling | Seth H. Pugsley, Roger Gramunt, Jonathan C. Hall, Prabhat Jain | 2018-06-26 |
| 9921972 | Method and apparatus for implementing a heterogeneous memory subsystem | Alaa R. Alameldeen, Zeshan A. Chishti, Jaewoong Sim | 2018-03-20 |
| 9921961 | Multi-level memory management | Alaa R. Alameldeen, Zhe Wang, Zeshan A. Chishti | 2018-03-20 |
| 9811555 | Recognition of free-form gestures from orientation tracking of a handheld or wearable device | Nicholas G. Mitri, Mariette Awad | 2017-11-07 |
| 9710391 | Methods and apparatuses for efficient load processing using buffers | Wei Liu, Youfeng Wu, Herbert Hum | 2017-07-18 |
| 9703708 | System and method for thread scheduling on reconfigurable processor cores | Alaa R. Alameldeen, Eugene Gorbatov, Zeshan A. Chishti | 2017-07-11 |
| 9678878 | Disabling cache portions during low voltage operations | Muhammad M. Khellah, Vivek K. De, Ming Zhang, Jaume Abella, Javier Carretero Casado +3 more | 2017-06-13 |
| 9594625 | Sequential circuit with error detection | Keith Alan Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Shih-Lien Linus Lu +2 more | 2017-03-14 |