Issued Patents All Time
Showing 51–75 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9583182 | Multi-level memory management | Alaa R. Alameldeen, Zhe Wang, Zeshan A. Chishti | 2017-02-28 |
| 9472248 | Method and apparatus for implementing a heterogeneous memory subsystem | Alaa R. Alameldeen, Zeshan A. Chishti, Jaewoong Sim | 2016-10-18 |
| 9417879 | Systems and methods for managing reconfigurable processor cores | Alaa R. Alameldeen, Eugene Gorbatov, Zeshan A. Chishti | 2016-08-16 |
| 9378021 | Instruction and logic for run-time evaluation of multiple prefetchers | Zeshan A. Chishti, Seth H. Pugsley, Peng-Fei Chuang, Robert L. Scott, Aamer Jaleel +2 more | 2016-06-28 |
| 9286224 | Constraining prefetch requests to a processor socket | Seth H. Pugsley, Robert L. Scott, Zeshan A. Chishti, Peng-Fei Chuang, Khun Ban +2 more | 2016-03-15 |
| 9229872 | Semiconductor chip with adaptive BIST cache testing during runtime | Jawad Nasrullah, Kelvin Kwan | 2016-01-05 |
| 9223710 | Read-write partitioning of cache memory | Alaa R. Alameldeen, Samira M. Khan | 2015-12-29 |
| 9189014 | Sequential circuit with error detection | Keith Alan Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Shih-Lien Linus Lu +2 more | 2015-11-17 |
| 8966345 | Selective error correction in memory to reduce power consumption | Alaa R. Alameldeen, Shih-Lien Linus Lu | 2015-02-24 |
| 8868836 | Reducing minimum operating voltage through hybrid cache design | Muhammad M. Khellah, Alaa R. Alameldeen, Bibiche M. Geuskens, Tanay Karnik, Vivek K. De +1 more | 2014-10-21 |
| 8848858 | Integrated non-volatile monotonic counters | James W. Tschanz, Scott H. Robinson, Shih-Lien Linus Lu | 2014-09-30 |
| 8806285 | Dynamically allocatable memory error mitigation | Alaa R. Alameldeen, Ilya Wagner, Zeshan A. Chishti, Wei Wu | 2014-08-12 |
| 8719502 | Adaptive self-repairing cache | Alaa R. Alameldeen, Jaydeep P. Kulkarni | 2014-05-06 |
| 8640005 | Method and apparatus for using cache memory in a system that supports a low power state | Alaa R. Alameldeen, Zeshan A. Chishti, Dinesh Somasekhar, Wei Wu, Shih-Lien Linus Lu | 2014-01-28 |
| 8452946 | Methods and apparatuses for efficient load processing using buffers | Wei Liu, Youfeng Wu, Herbert Hum | 2013-05-28 |
| 8291168 | Disabling cache portions during low voltage operations | Muhammad M. Khellah, Vivek K. De, Ming Zhang, Jaume Abella, Javier Carretero Casado +3 more | 2012-10-16 |
| 8103830 | Disabling cache portions during low voltage operations | Muhammad M. Khellah, Vivek K. De, Ming Zhang, Jaume Abella, Javier Carretero Casado +3 more | 2012-01-24 |
| 7206918 | Address predicting apparatus and methods | Wayne Wong | 2007-04-17 |
| 7114059 | System and method to bypass execution of instructions involving unreliable data during speculative execution | — | 2006-09-26 |
| 7111132 | Parallel processing apparatus, system, and method utilizing correlated data value pairs | — | 2006-09-19 |
| 6957304 | Runahead allocation protection (RAP) | — | 2005-10-18 |
| 6954848 | Marking in history table instructions slowable/delayable for subsequent executions when result is not used immediately | Ryan Rakvic, Bryan Black, Edward T. Grochowski, John Shen, Edward A. Brekelbaum | 2005-10-11 |
| 6931490 | Set address correlation address predictors for long memory latencies | Wayne Wong | 2005-08-16 |
| 6785797 | Address predicting apparatus and methods | Wayne Wong | 2004-08-31 |
| 6782469 | Runtime critical load/data ordering | Srikanth Srinivasan, Dz-ching Ju | 2004-08-24 |