Issued Patents All Time
Showing 26–50 of 194 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8531205 | Programmable output buffer | Bonnie I. Wang, Xiaobao Wang, Khai Nguyen, Joseph Huang | 2013-09-10 |
| 8487665 | Programmable high-speed interface | Bonnie I. Wang, Joseph Huang, Khai Nguyen, Philip Pan | 2013-07-16 |
| 8476947 | Duty cycle distortion correction circuitry | John Henry Bui, Lay Hock Khoo, Khai Nguyen, Ket Chiew Sia | 2013-07-02 |
| 8400186 | Techniques for buffering single-ended and differential signals | Xiaobao Wang, Joseph Huang, Khai Nguyen | 2013-03-19 |
| 8390315 | Configurable input-output (I/O) circuitry with pre-emphasis circuitry | Xiaobao Wang, Joseph Huang, Khai Nguyen | 2013-03-05 |
| 8384460 | Techniques for phase adjustment | John Henry Bui, Khai Nguyen, Bonnie I. Wang, Xiaobao Wang | 2013-02-26 |
| 8368449 | Dead zone detection for phase adjustment | John Henry Bui, Khai Nguyen | 2013-02-05 |
| 8305121 | High-performance memory interface circuit architecture | Joseph Huang, Philip Pan, Yan Chong, Andy L. Lee, Brian Johnson | 2012-11-06 |
| 8237475 | Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop | Pradeep Nagarajan, Sean Shau-Tu Lu, Joseph Huang, Yan Chong | 2012-08-07 |
| 8159277 | Techniques for providing multiple delay paths in a delay circuit | Pradeep Nagarajan, Yan Chong, Joseph Huang | 2012-04-17 |
| 8149038 | Techniques for phase adjustment | John Henry Bui, Khai Nguyen, Bonnie I. Wang, Xiaobao Wang | 2012-04-03 |
| 8130016 | Techniques for providing reduced duty cycle distortion | Pradeep Nagarajan, Yan Chong, Joseph Huang | 2012-03-06 |
| 8122275 | Write-leveling implementation in programmable logic devices | Yan Chong, Bonnie I. Wang, Joseph Huang, Michael H. M. Chu | 2012-02-21 |
| 8098082 | Multiple data rate interface architecture | Philip Pan, Joseph Huang, Yan Chong, Bonnie I. Wang | 2012-01-17 |
| 8022723 | Dynamic termination-impedance control for bidirectional I/O pins | Xiaobao Wang, Bonnie I. Wang, Khai Nguyen | 2011-09-20 |
| 7994821 | Level shifter circuits and methods | Xiaobao Wang, Khai Nguyen | 2011-08-09 |
| 7990786 | Read-leveling implementations for DDR3 applications on an FPGA | Michael H. M. Chu, Joseph Huang, Yan Chong, Andrew Bellis, Philip Clarke +1 more | 2011-08-02 |
| 7973553 | Techniques for on-chip termination | Xiaobao Wang, Bonnie I. Wang, Khai Nguyen, John Henry Bui | 2011-07-05 |
| 7969215 | High-performance memory interface circuit architecture | Joseph Huang, Philip Pan, Yan Chong, Andy L. Lee, Brian Johnson | 2011-06-28 |
| 7893739 | Techniques for providing multiple delay paths in a delay circuit | Pradeep Nagarajan, Yan Chong, Joseph Huang | 2011-02-22 |
| 7884619 | Method and apparatus for minimizing skew between signals | Yan Chong, Joseph Huang, Eric Choong-Yin Chang, Peter Boyle, Adam Wright | 2011-02-08 |
| 7859304 | Multiple data rate interface architecture | Philip Pan, Joseph Huang, Yan Chong, Bonnie I. Wang | 2010-12-28 |
| 7825682 | Techniques for providing adjustable on-chip termination impedance | Xiaobao Wang, Khai Nguyen, Sanjay K. Charagulla | 2010-11-02 |
| 7746134 | Digitally controlled delay-locked loops | Sean Shau-Tu Lu, Joseph Huang, Yan Chong | 2010-06-29 |
| 7725755 | Self-compensating delay chain for multiple-date-rate interfaces | Yan Chong, Bonnie I. Wang, Joseph Huang, Xiaobao Wang, Philip Pan +1 more | 2010-05-25 |