Issued Patents All Time
Showing 51–75 of 194 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7710149 | Input buffer for multiple differential I/O standards | Jonathan Chung, In Whan Kim, Philip Pan, Bonnie I. Wang, Xiabao Wang +5 more | 2010-05-04 |
| 7706996 | Write-side calibration for data interface | Yan Chong, Joseph Huang, Michael H. M. Chu | 2010-04-27 |
| 7671579 | Method and apparatus for quantifying and minimizing skew between signals | Yan Chong, Joseph Huang, Eric Choong-Yin Chang, Peter Boyle, Adam Wright | 2010-03-02 |
| 7593273 | Read-leveling implementations for DDR3 applications on an FPGA | Michael H. M. Chu, Joseph Huang, Yan Chong, Andrew Bellis, Philip Clarke +1 more | 2009-09-22 |
| 7590879 | Clock edge de-skew | Henry Kim, Bonnie I. Wang, Joseph Huang | 2009-09-15 |
| 7589556 | Dynamic control of memory interface timing | Johnson Tan, Andrew Bellis, Philip Clarke, Yan Chong, Joseph Huang +1 more | 2009-09-15 |
| 7586341 | Programmable high-speed interface | Bonnie Wang, Joseph Huang, Khai Nguyen, Philip Pan | 2009-09-08 |
| 7551014 | Differential output with low output skew | Bonnie I. Wang, Khai Nguyen, Xiaobao Wang | 2009-06-23 |
| 7535275 | High-performance memory interface circuit architecture | Joseph Huang, Philip Pan, Yan Chong, Andy L. Lee, Brian Johnson | 2009-05-19 |
| 7525360 | I/O duty cycle and skew control | Xiaobao Wang, Khai Nguyen | 2009-04-28 |
| 7509223 | Read-side calibration for data interface | Yan Chong, Joseph Huang, Michael H. M. Chu | 2009-03-24 |
| 7492185 | Innovated technique to reduce memory interface write mode SSN in FPGA | Joseph Huang, Michael H. M. Chu, Yan Chong | 2009-02-17 |
| 7477074 | Multiple data rate interface architecture | Philip Pan, Joseph Huang, Yan Chong, Bonnie I. Wang | 2009-01-13 |
| 7425844 | Input buffer for multiple differential I/O standards | Jonathan Chung, In Whan Kim, Philip Pan, Bonnie I. Wang, Xiaobao Wang +5 more | 2008-09-16 |
| 7420386 | Techniques for providing flexible on-chip termination control on integrated circuits | Xiaobao Wang, Khai Nguyen | 2008-09-02 |
| 7417452 | Techniques for providing adjustable on-chip termination impedance | Xiaobao Wang, Khai Nguyen, Sanjay K. Charagulla | 2008-08-26 |
| 7378868 | Modular I/O bank architecture | Jeffrey Tyhach, Khai Nguyen, Sanjay K. Charagulla, Ali Burney | 2008-05-27 |
| 7358783 | Voltage, temperature, and process independent programmable phase shift for PLL | Bonnie I. Wang, Joseph Huang, Xiaobao Wang, In Whan Kim, Wayne Yeung +1 more | 2008-04-15 |
| 7330051 | Innovated technique to reduce memory interface write mode SSN in FPGA | Joseph Huang, Michael H. M. Chu, Yan Chong | 2008-02-12 |
| 7324405 | DQS postamble filtering | Sanjay K. Charagulla, Joseph Huang, Bonnie I. Wang, Yan Chong | 2008-01-29 |
| 7321518 | Apparatus and methods for providing redundancy in integrated circuits | Joseph Huang, Philip Pan, Yan Chong | 2008-01-22 |
| 7315188 | Programmable high speed interface | Bonnie Wang, Joseph Huang, Khai Nguyen, Philip Pan | 2008-01-01 |
| 7309906 | Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices | Jeffrey Tyhach, Bonnie I. Wang, Yan Chong | 2007-12-18 |
| 7304501 | Method and apparatus for protecting a circuit during a hot socket condition | Xiaobao Wang, Khai Nguyen, Bonnie I. Wang | 2007-12-04 |
| 7295040 | High speed IO buffer using auxiliary power supply | Khai Nguyen, Gopi Rangan, Tzung-Chin Chang | 2007-11-13 |