CJ

Chia-Hong Jan

IN Intel: 144 patents #100 of 30,777Top 1%
TR Tahoe Research: 1 patents #81 of 215Top 40%
WARF: 1 patents #1,912 of 4,123Top 50%
📍 Portland, OR: #52 of 9,213 inventorsTop 1%
🗺 Oregon: #100 of 28,073 inventorsTop 1%
Overall (All Time): #6,417 of 4,157,543Top 1%
147
Patents All Time

Issued Patents All Time

Showing 126–147 of 147 patents

Patent #TitleCo-InventorsDate
6521964 Device having spacers for improved salicide resistance on polysilicon gates Julie Tsai, Simon Shi-Ning Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating +1 more 2003-02-18
6518155 Device structure and method for reducing silicide encroachment Robert S. Chau, Ebrahim Andideh, Mitch Taylor, Julie Tsai 2003-02-11
6509618 Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates Julie Tsai, Simon Shi-Ning Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating +1 more 2003-01-21
6506652 Method of recessing spacers to improved salicide resistance on polysilicon gates Julie Tsai, Simon Shi-Ning Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating +1 more 2003-01-14
6479391 Method for making a dual damascene interconnect using a multilayer hard mask Patrick Morrow, Jihperng Leu 2002-11-12
6326664 Transistor with ultra shallow tip and method of fabrication Robert S. Chau, Chan-Hong Chern, Kevin R. Weldon, Paul Packan, Leopoldo D. Yau 2001-12-04
6271096 Method and device for improved salicide resistance on polysilicon gates Julie Tsai, Simon Shi-Ning Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating +1 more 2001-08-07
6268254 Method and device for improved salicide resistance on polysilicon gates Julie Tsai, Simon Shi-Ning Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating +1 more 2001-07-31
6251762 Method and device for improved salicide resistance on polysilicon gates Julie Tsai, Simon Shi-Ning Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating +1 more 2001-06-26
6235568 Semiconductor device having deposited silicon regions and a method of fabrication Anand S. Murthy, Ebrahim Andideh, Kevin R. Weldon 2001-05-22
6235598 Method of using thick first spacers to improve salicide resistance on polysilicon gates Julie Tsai, Simon Shi-Ning Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating +1 more 2001-05-22
6198142 Transistor with minimal junction capacitance and method of fabrication Robert S. Chau, Paul Packan, Mitchell Taylor 2001-03-06
6188117 Method and device for improved salicide resistance on polysilicon gates Julie Tsai, Simon Shi-Ning Yang, Tahir Ghani, Kevin A. Whitehill, Steven J. Keating +1 more 2001-02-13
6165826 Transistor with low resistance tip and method of fabrication in a CMOS process Robert S. Chau, Chan-Hong Chern, Leopoldo D. Yau 2000-12-26
6121100 Method of fabricating a MOS transistor with a raised source/drain extension Ebrahim Andideh, Lawrence N. Brigham, Robert S. Chau, Tahir Ghani, Justin S. Sandford +1 more 2000-09-19
6114722 Microcrystalline silicon structure and fabrication process Sean Corcoran 2000-09-05
6017819 Method for forming a polysilicon/amorphous silicon composite gate electrode Lawrence N. Brigham, Binglong Zhang 2000-01-25
5908313 Method of forming a transistor Robert S. Chau, Paul Packan, Mitchell Taylor 1999-06-01
5891809 Manufacturable dielectric formed using multiple oxidation and anneal steps Robert S. Chau, Lawrence N. Brigham, Chan-Hong Chern, Binny Arcot 1999-04-06
5885884 Process for fabricating a microcrystalline silicon structure Sean Corcoran 1999-03-23
5710450 Transistor with ultra shallow tip and method of fabrication Robert S. Chau, Chan-Hong Chern, Kevin R. Weldon, Paul Packan, Leopoldo D. Yau 1998-01-20
5516725 Process for preparing schottky diode contacts with predetermined barrier heights Y. Austin Chang, Chia-Ping Chen 1996-05-14