Issued Patents All Time
Showing 51–75 of 86 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7871916 | Transistor gate electrode having conductor material layer | Anand S. Murthy, Boyan Boyanov, Suman Datta, Brian S. Doyle, Shaofeng Yu +1 more | 2011-01-18 |
| 7851790 | Isolated Germanium nanowire on Silicon fin | Willy Rachmady, Ravi Pillarisetty, Robert S. Chau | 2010-12-14 |
| 7825400 | Strain-inducing semiconductor regions | Suman Datta, Jack T. Kavalieros | 2010-11-02 |
| 7821061 | Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications | Brian S. Doyle, Jack T. Kavalieros, Robert S. Chau | 2010-10-26 |
| 7767560 | Three dimensional strained quantum wells and three dimensional strained surface channels by Ge confinement method | Robert S. Chau, Brian S. Doyle, Jack T. Kavalieros | 2010-08-03 |
| 7745270 | Tri-gate patterning using dual layer gate stack | Uday Shah, Brian S. Doyle, Jack T. Kavalieros | 2010-06-29 |
| 7727830 | Fabrication of germanium nanowire transistors | Jack T. Kavalieros, Matthew V. Metz, Marko Radosavlievic, Robert S. Chau | 2010-06-01 |
| 7713803 | Mechanism for forming a remote delta doping layer of a quantum well structure | Jack T. Kavalieros, Suman Datta, Amlan Majumdar, Robert S. Chau | 2010-05-11 |
| 7714397 | Tri-gate transistor device with stress incorporation layer and method of fabrication | Scott A. Hareland, Robert S. Chau, Brian S. Doyle, Suman Datta | 2010-05-11 |
| 7709312 | Methods for inducing strain in non-planar transistor structures | Brian S. Doyle, Uday Shah, Jack T. Kavalieros | 2010-05-04 |
| 7671414 | Semiconductor on insulator apparatus | Reza Arghavani, Robert S. Chau | 2010-03-02 |
| 7642610 | Transistor gate electrode having conductor material layer | Anand S. Murthy, Boyan Boyanov, Suman Datta, Brian S. Doyle, Shaofeng Yu +1 more | 2010-01-05 |
| 7638383 | Faceted catalytic dots for directed nanotube growth | Robert S. Chau, Brian S. Doyle, Marko Radosavljevic | 2009-12-29 |
| 7592213 | Tensile strained NMOS transistor using group III-N source/drain regions | Suman Datta, Justin K. Brask, Jack T. Kavalieros, Mantu K. Hudait | 2009-09-22 |
| 7569869 | Transistor having tensile strained channel and system including same | Robert S. Chau, Suman Datta, Jack T. Kavalieros, Marko Radosavlievic | 2009-08-04 |
| 7553687 | Dual seed semiconductor photodetectors | Miriam Reshotko | 2009-06-30 |
| 7531393 | Non-planar MOS structure with a strained channel region | Brian S. Doyle, Suman Datta, Robert S. Chau | 2009-05-12 |
| 7521775 | Protection of three dimensional transistor structures during gate stack etch | Brian S. Doyle, Uday Shah, Jack T. Kavalieros | 2009-04-21 |
| 7485536 | Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers | Brian S. Doyle, Robert S. Chau, Jack T. Kavalieros | 2009-02-03 |
| 7470972 | Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress | Jack T. Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta +7 more | 2008-12-30 |
| 7427538 | Semiconductor on insulator apparatus and method | Reza Arghavani, Robert S. Chau | 2008-09-23 |
| 7348284 | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow | Brian S. Doyle, Suman Datta, Nancy Zelick, Robert S. Chau | 2008-03-25 |
| 7268058 | Tri-gate transistors and methods to fabricate same | Robert S. Chau, Suman Datta, Brian S. Doyle | 2007-09-11 |
| 7241653 | Nonplanar device with stress incorporation layer and method of fabrication | Scott A. Hareland, Robert S. Chau, Brian S. Doyle, Suman Datta | 2007-07-10 |
| 7235809 | Semiconductor channel on insulator structure | Brian S. Doyle, Scott A. Hareland, Mark L. Doczy, Matthew V. Metz, Boyan Boyanov +3 more | 2007-06-26 |