AK

Akhilesh Kumar

IN Intel: 35 patents #1,016 of 30,777Top 4%
Adobe: 10 patents #366 of 4,589Top 8%
AN Ansys: 7 patents #8 of 298Top 3%
WARF: 4 patents #486 of 4,123Top 15%
SS Sap Se: 2 patents #1,751 of 6,322Top 30%
TE Toyo Engineering: 1 patents #103 of 295Top 35%
HT Hsbc Technologies: 1 patents #2 of 28Top 8%
📍 Milpitas, CA: #49 of 3,192 inventorsTop 2%
🗺 California: #5,623 of 386,348 inventorsTop 2%
Overall (All Time): #37,462 of 4,157,543Top 1%
61
Patents All Time

Issued Patents All Time

Showing 26–50 of 61 patents

Patent #TitleCo-InventorsDate
9887849 Reduced wake up delay for on-die routers Dongkook Park, Donglai Dai 2018-02-06
9868939 Generating vasculogenic cell populations Igor I. Slukvin 2018-01-16
9798556 Method, system, and apparatus for dynamic reconfiguration of resources Mani Ayyar, Eric Delano, Ioannis Schoinas, Doddaballapur N. Jayasimha, Jose A. Vargas 2017-10-24
9674114 Modular decoupled crossbar for on-chip router Dongkook Park, Aniruddha Vaidya, Mani Azimi 2017-06-06
9418011 Region based technique for accurately predicting memory accesses Livio B. Soares, Naveen Cherukuri, Mani Azimi 2016-08-16
9250679 Reduced wake up delay for on-die routers Dongkook Park, Donglai Dai 2016-02-02
9223738 Method, system, and apparatus for dynamic reconfiguration of resources Mani Ayyar, Eric Delano, Ioannis Schoinas, Doddaballapur N. Jayasimha, Jose A. Vargas 2015-12-29
8990506 Replacing cache lines in a cache memory based at least in part on cache coherency state information Naveen Cherukuri, Dennis W. Brzezinski, Ioannis T. Schoinas, Anahita Shayesteh, Mani Azimi 2015-03-24
8606934 Method, system, and apparatus for system level initialization by conveying capabilities and identifiers of components Mani Ayyar, Srinivas Chennupaty, Doddabaliapur Narasimha-Murthy Jayasimha, Murugasamy Nachimuthu, Phanindra Kumar Mannava +1 more 2013-12-10
8327113 Method, system, and apparatus for dynamic reconfiguration of resources Mani Ayyar, Eric Delano, Ioannis T. Schoinas, Jay Jayasimha, Jose A. Vargas 2012-12-04
8190820 Optimizing concurrent accesses in a directory-based coherency protocol Hariharan Lakshminarayanan Thantry, Seungjoon Park 2012-05-29
8171121 Method, system, and apparatus for dynamic reconfiguration of resources Mani Ayyar, Eric Delano, Ioannis T. Schoinas, Jay Jayasimha, Jose A. Vargas 2012-05-01
8141140 Methods and systems for single sign on with dynamic authentication levels Roberto Wenzel, Alexander Kalinovsky, Justin Michael Billinghay, Aditya Kommaraju, Suresh Madhavan +3 more 2012-03-20
8099558 Fairness mechanism for starvation prevention in directory-based cache coherence protocols Seungjoon Park, Ching-Tsun Chou 2012-01-17
7996625 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture Manoj Khare, Faye A. Briggs, Lily P. Looi, Kai Cheng 2011-08-09
7991875 Link level retry scheme Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Phanindra Kumar Mannava, Rajee Ram +3 more 2011-08-02
7738484 Method, system, and apparatus for system level initialization Mani Ayyar, Srinivas Chennupaty, Doddaballapur N. Jayasimha, Murugasamy Nachimuthu, Phanindra Kumar Mannava 2010-06-15
7734741 Method, system, and apparatus for dynamic reconfiguration of resources Mani Ayyar, Eric Delano, Ioannis T. Schoinas, Jay Jayasimha, Jose A. Vargas 2010-06-08
7433985 Conditional and vectored system management interrupts Mani Ayyar, Ioannis T. Schoinas, Rama Menon, Aniruddha Vaidya 2008-10-07
7370135 Band configuration agent for link based computing system Eric Delano, Ioannis Schoinas, Doddaballapur N. Jayasimha 2008-05-06
7328368 Dynamic interconnect width reduction to improve interconnect availability Phanindra Kumar Mannava, Victor W. Lee, Doddaballapur N. Jayasimha, Ioannis T. Schoinas 2008-02-05
7320094 Retraining derived clock receivers Victor W. Lee, Phanindra Kumar Mannava, Sanjay Dabral 2008-01-15
7310972 Process and apparatus for separation of hydrocarbons from liquefied natural gas Nobuhiro Yoshida, Shoichi Yamaguchi, Susumu Ohara 2007-12-25
7234029 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture Manoj Khare, Faye A. Briggs, Lily P. Looi, Kai Cheng 2007-06-19
7167957 Mechanism for handling explicit writeback in a cache coherent multi-node architecture Manoj Khare, Lily P. Looi 2007-01-23