Issued Patents All Time
Showing 51–61 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7124252 | Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system | Manoj Khare, Lily P. Looi, Kenneth C. Creta | 2006-10-17 |
| 7016304 | Link level retry scheme | Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Phanindra Kumar Mannava, Rajee Ram +3 more | 2006-03-21 |
| 6976129 | Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture | Kenneth C. Creta, Manoj Khare, Lily P. Looi | 2005-12-13 |
| 6971098 | Method and apparatus for managing transaction requests in a multi-node architecture | Manoj Khare, Ioannis T. Schoinas, Lily P. Looi | 2005-11-29 |
| 6859864 | Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line | Manoj Khare, Lily P. Looi, Kenneth C. Creta | 2005-02-22 |
| 6842830 | Mechanism for handling explicit writeback in a cache coherent multi-node architecture | Manoj Khare, Lily P. Looi | 2005-01-11 |
| 6826619 | Method and apparatus for preventing starvation in a multi-node architecture | Manoj Khare, Sin S. Tan | 2004-11-30 |
| 6772298 | Method and apparatus for invalidating a cache line without data return in a multi-node architecture | Manoj Khare, Ken Creta, Lily P. Looi, Robert T. George, Michel Cekleov | 2004-08-03 |
| 6622215 | Mechanism for handling conflicts in a multi-node computer architecture | Manoj Khare, Lily P. Looi, Sin S. Tan | 2003-09-16 |
| 6615319 | Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architecture | Manoj Khare, Lily P. Looi, Faye A. Briggs | 2003-09-02 |
| 6487643 | Method and apparatus for preventing starvation in a multi-node architecture | Manoj Khare | 2002-11-26 |