Issued Patents All Time
Showing 51–75 of 108 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9900970 | Three dimensional integrated circuit electrostatic discharge protection and prevention test interface | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin | 2018-02-20 |
| 9891266 | Test circuit and method | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang | 2018-02-13 |
| 9880201 | Systems for probing semiconductor wafers | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin | 2018-01-30 |
| 9859176 | Semiconductor device, test system and method of the same | Tang-Jung Chiu, Mill-Jer Wang, Hung-Chih Lin | 2018-01-02 |
| 9754847 | Circuit probing structures and methods for probing the same | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin | 2017-09-05 |
| 9739865 | Identification method and identification system for an object's passing route direction | Jian Wu, Jianqiang Zeng | 2017-08-22 |
| 9671457 | 3D IC testing apparatus | Mill-Jer Wang, Chih-Chia Chen, Hung-Chih Lin, Ching-Nen Peng | 2017-06-06 |
| 9664707 | Testing holders for chip unit and die package | Mill-Jer Wang, Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin | 2017-05-30 |
| 9658281 | Alignment testing for tiered semiconductor structure | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Mincent Lee | 2017-05-23 |
| 9653927 | Composite integrated circuits and methods for wireless interactions therewith | Min-Jer Wang, Ching-Nen Peng, Chewn-Pu Jou, Feng-Wei Kuo, Hung-Chih Lin +4 more | 2017-05-16 |
| 9640447 | Test circuit and method | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Chung-Han Huang | 2017-05-02 |
| 9606155 | Capacitance measurement circuit and method | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Chung-Han Huang | 2017-03-28 |
| 9568543 | Structure and method for testing stacked CMOS structure | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin | 2017-02-14 |
| 9455348 | FinFET for device characterization | Chang-Yun Chang, Cheng-Chuan Huang, Fu-Liang Yang | 2016-09-27 |
| 9453877 | Testing holders for chip unit and die package | Mill-Jer Wang, Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin | 2016-09-27 |
| 9448285 | Method and apparatus of wafer testing | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Shang-Ju Lee | 2016-09-20 |
| 9417285 | Integrated fan-out package-on-package testing | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin | 2016-08-16 |
| 9372227 | Integrated circuit test system and method | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Wei-Hsun Lin, Chung-Han Huang | 2016-06-21 |
| 9341671 | Testing holders for chip unit and die package | Mill-Jer Wang, Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin | 2016-05-17 |
| 9310437 | Adaptive test sequence for testing integrated circuits | Chun-Cheng Chen, Hung-Chih Lin, Mill-Jer Wang, Ching-Nen Peng | 2016-04-12 |
| 9258618 | Channelization method of digital content and audio-video server system | Chung-Chi Chang, I-Cheng He, Kuang-Min Hsu | 2016-02-09 |
| 9252593 | Three dimensional integrated circuit electrostatic discharge protection and prevention test interface | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin | 2016-02-02 |
| 9234940 | Integrated fan-out wafer architecture and test method | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin | 2016-01-12 |
| 9129973 | Circuit probing structures and methods for probing the same | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin | 2015-09-08 |
| 9086452 | Three-dimensional integrated circuit and method for wireless information access thereof | Mill-Jer Wang, Chewn-Pu Jou, Ching-Nen Peng, Huan-Neng Chen, Hung-Chih Lin +4 more | 2015-07-21 |