Issued Patents All Time
Showing 76–100 of 108 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8957691 | Probe cards for probing integrated circuits | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin | 2015-02-17 |
| 8956889 | Method of testing through silicon VIAS (TSVs) of three dimensional integrated circuit (3DIC) | Hung-Chih Lin, Mill-Jer Wang, Ching-Nen Peng | 2015-02-17 |
| 8952711 | Methods for probing semiconductor wafers | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin | 2015-02-10 |
| 8922230 | 3D IC testing apparatus | Mill-Jer Wang, Chih-Chia Chen, Hung-Chih Lin, Ching-Nen Peng | 2014-12-30 |
| 8866488 | Power compensation in 3DIC testing | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin | 2014-10-21 |
| 8865539 | Fully depleted SOI multiple threshold voltage application | Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang | 2014-10-21 |
| 8836355 | Dynamic testing based on thermal and stress conditions | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin | 2014-09-16 |
| 8790970 | Doping of semiconductor fin devices | Yee-Chia Yeo, Ping-Wei Wang, Fu-Liang Yang, Chenming Hu | 2014-07-29 |
| 8614105 | Production flow and reusable testing method | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin | 2013-12-24 |
| 8421073 | Test structures for through silicon vias (TSVs) of three dimensional integrated circuit (3DIC) | Hung-Chih Lin, Mill-Jer Wang, Ching-Nen Peng | 2013-04-16 |
| 8053839 | Doping of semiconductor fin devices | Yee-Chia Yeo, Ping-Wei Wang, Fu-Liang Yang, Chenming Hu | 2011-11-08 |
| 8049300 | Inductor energy loss reduction techniques | Andrew S. Yeh, Alex Chang, Sung-Pi Tseng, Chang-Yun Chang, Fu-Liang Yang | 2011-11-01 |
| 7948037 | Multiple-gate transistor structure and method for fabricating | Yee-Chia Yeo, Fu-Liang Yang | 2011-05-24 |
| 7728360 | Multiple-gate transistor structure | Yee-Chia Yeo, Fu-Liang Yang | 2010-06-01 |
| 7701008 | Doping of semiconductor fin devices | Yee-Chia Yeo, Ping-Wei Wang, Fu-Liang Yang, Chenming Hu | 2010-04-20 |
| 7638376 | Method for forming SOI device | Cheng-Kuo Wen, Chien-Chao Huang, Fu-Liang Yang, Hsun-Chih Tsao | 2009-12-29 |
| 7635632 | Gate electrode for a semiconductor fin device | Yee-Chia Yeo, Fu-Liang Yang, Chenming Hu | 2009-12-22 |
| 7608515 | Diffusion layer for stressed semiconductor devices | Shui-Ming Cheng | 2009-10-27 |
| 7585711 | Semiconductor-on-insulator (SOI) strained active area transistor | Fu-Liang Yang | 2009-09-08 |
| 7485929 | Semiconductor-on-insulator (SOI) strained active areas | Fu-Liang Yang | 2009-02-03 |
| 7423323 | Semiconductor device with raised segment | Yee-Chia Yeo, Fu-Liang Yang, Chenming Hu | 2008-09-09 |
| 7382023 | Fully depleted SOI multiple threshold voltage application | Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang | 2008-06-03 |
| 7230270 | Self-aligned double gate device and method for forming same | Ju-Wang Hsu, Baw-Ching Perng, Fu-Liang Yang | 2007-06-12 |
| 7176092 | Gate electrode for a semiconductor fin device | Yee-Chia Yeo, Fu-Liang Yang, Chenming Hu | 2007-02-13 |
| 7141459 | Silicon-on-insulator ULSI devices with multiple silicon film thicknesses | Fu-Liang Yang, Yee-Chia Yeo, Carlos H. Diaz, Chenming Hu | 2006-11-28 |