Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12334854 | Power integrated module and motor control system | Shian-Chiau Chiou, Yu-Hua Cheng | 2025-06-17 |
| 10672677 | Semiconductor package structure | Jing-Yao Chang, Tao-Chih Chang, Kuo-Shu Kao, Fang-Jun Leu, Hsin-Han Lin +2 more | 2020-06-02 |
| 10288696 | Intelligent diagnosis system for power module and method thereof | Chih-Chung Chiu, Li-Ling Liao, Yu-Lin Chao, Chih-Ming Shen, Ming-Kaan Liang +2 more | 2019-05-14 |
| 9601474 | Electrically stackable semiconductor wafer and chip packages | Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Jyh-Rong Lin +1 more | 2017-03-21 |
| 9059181 | Wafer leveled chip packaging structure and method thereof | Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Jyh-Rong Lin +1 more | 2015-06-16 |
| 8587091 | Wafer-leveled chip packaging structure and method thereof | Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Jyh-Rong Lin +1 more | 2013-11-19 |
| 8314482 | Semiconductor package device | Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Jyh-Rong Lin +1 more | 2012-11-20 |
| 7528009 | Wafer-leveled chip packaging structure and method thereof | Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Jyh-Rong Lin +1 more | 2009-05-05 |
| 7294920 | Wafer-leveled chip packaging structure and method thereof | Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Jyh-Rong Lin +1 more | 2007-11-13 |