Issued Patents All Time
Showing 101–125 of 150 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853054 | Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation | Kangguo Cheng, Juntao Li, Xin Miao | 2017-12-26 |
| 9809233 | Vehicle body and manufacturing method | Harold Kendall, Daniel Ganzer, Aiqin Jiang | 2017-11-07 |
| 9806155 | Split fin field effect transistor enabling back bias on fin type field effect transistors | Veeraraghavan S. Basker, Xin Miao, Tenko Yamashita | 2017-10-31 |
| 9805989 | Sacrificial cap for forming semiconductor contact | Praneet Adusumilli, Shogo Mochizuki, Jie Yang, Chun Wing Yeung | 2017-10-31 |
| 9805973 | Dual silicide liner flow for enabling low contact resistance | Praneet Adusumilli, Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh | 2017-10-31 |
| 9773709 | Forming CMOSFET structures with different contact liners | Kangguo Cheng, Tenko Yamashita | 2017-09-26 |
| 9768077 | Low resistance dual liner contacts for Fin Field-Effect Transistors (FinFETs) | Praneet Adusumilli, Veeraraghavan S. Basker | 2017-09-19 |
| 9768027 | FinFET having controlled dielectric region height | Dechao Guo, Tenko Yamashita, Chun-Chen Yeh | 2017-09-19 |
| 9768085 | Top contact resistance measurement in vertical FETs | Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang | 2017-09-19 |
| 9741813 | Pure boron for silicide contact | Chia-Yu Chen, Sanjay C. Mehta, Tenko Yamashita | 2017-08-22 |
| 9735248 | Pure boron for silicide contact | Chia-Yu Chen, Sanjay C. Mehta, Tenko Yamashita | 2017-08-15 |
| 9728537 | Dual fin integration for electron and hole mobility enhancement | Chia-Yu Chen, Miaomiao Wang, Tenko Yamashita | 2017-08-08 |
| 9711645 | Method and structure for multigate FinFET device epi-extension junction control by hydrogen treatment | Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh | 2017-07-18 |
| 9704867 | Dual fin integration for electron and hole mobility enhancement | Chia-Yu Chen, Miaomiao Wang, Tenko Yamashita | 2017-07-11 |
| 9704754 | Self-aligned spacer for cut-last transistor fabrication | Ruqiang Bao, Dechao Guo | 2017-07-11 |
| 9680020 | Increased contact area for FinFETs | Veeraraghavan S. Basker, Chung-Hsun Lin, Tenko Yamashita, Chun-Chen Yeh | 2017-06-13 |
| 9673293 | Airgap spacers | Kangguo Cheng, Chun Wing Yeung | 2017-06-06 |
| 9659960 | Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation | Kangguo Cheng, Juntao Li, Xin Miao | 2017-05-23 |
| 9647062 | Silicon nanowire formation in replacement metal gate process | Chia-Yu Chen, Tenko Yamashita | 2017-05-09 |
| 9620644 | Composite spacer enabling uniform doping in recessed fin devices | Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh | 2017-04-11 |
| 9607900 | Method and structure to fabricate closely packed hybrid nanowires at scaled pitch | Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh | 2017-03-28 |
| 9608069 | Self aligned epitaxial based punch through control | Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh | 2017-03-28 |
| 9601621 | Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain | Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh | 2017-03-21 |
| 9595597 | Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain | Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh | 2017-03-14 |
| 9570574 | Recessed metal liner contact with copper fill | Praneet Adusumilli, Veeraraghavan S. Basker, Huiming Bu | 2017-02-14 |