TS

Timothy J. Slegel

IBM: 414 patents #39 of 70,183Top 1%
📍 Staatsburg, NY: #1 of 55 inventorsTop 2%
🗺 New York: #29 of 115,490 inventorsTop 1%
Overall (All Time): #582 of 4,157,543Top 1%
414
Patents All Time

Issued Patents All Time

Showing 26–50 of 414 patents

Patent #TitleCo-InventorsDate
11080064 Instructions controlling access to shared registers of a multi-threaded processor Giora Biran, Fadi Y. Busaba, Ophir Erez, Mark S. Farrell, Lisa C. Heller +2 more 2021-08-03
11080087 Transaction begin/end instructions Dan F. Greiner, Christian Jacobi, Marcel Mitran 2021-08-03
11080052 Determining the effectiveness of prefetch instructions Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum 2021-08-03
11061685 Extended asynchronous data mover functions compatibility indication Louis P. Gomes, Bruce C. Giamei, Mark S. Farrell, Matthias Klein 2021-07-13
11061684 Architecturally paired spill/reload multiple instructions for suppressing a snapshot latest value determination Michael K. Gschwind, Chung-Lung K. Shum 2021-07-13
11061680 Instructions controlling access to shared registers of a multi-threaded processor Giora Biran, Fadi Y. Busaba, Ophir Erez, Mark S. Farrell, Lisa C. Heller +2 more 2021-07-13
11031951 Verifying the correctness of a deflate compression accelerator Mark S. Farrell, Bruce C. Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt +1 more 2021-06-08
11010192 Register restoration using recovery buffers Michael K. Gschwind, Chung-Lung K. Shum 2021-05-18
11010066 Identifying processor attributes based on detecting a guarded storage event Dan F. Greiner, Christian Jacobi, Marcel Mitran, Volodymyr Paprotski, Anthony Saporito 2021-05-18
10977190 Dynamic address translation with access control in an emulator environment Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer +1 more 2021-04-13
10963391 Extract target cache attribute facility and instruction therefor Dan F. Greiner 2021-03-30
10956156 Conditional transaction end instruction Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt 2021-03-23
10929130 Guarded storage event handling during transactional execution Dan F. Greiner, Christian Jacobi, Volodymyr Paprotski, Anthony Saporito, Chung-Lung K. Shum 2021-02-23
10915439 Prefetch insensitive transactional memory Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum 2021-02-09
10908903 Efficiency for coordinated start interpretive execution exit for a multithreaded processor Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more 2021-02-02
10901736 Conditional instruction end operation Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt 2021-01-26
10884946 Memory state indicator check operations Pak-kin Mak, Craig R. Walters, Charles F. Webb 2021-01-05
10884945 Memory state indicator check operations Pak-kin Mak, Craig R. Walters, Charles F. Webb 2021-01-05
10884931 Interprocessor memory status communication Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum 2021-01-05
10838631 Detection of alteration of storage keys used to protect memory Jonathan D. Bradbury, Bruce C. Giamei, James H. Mulder, Peter J. Relson 2020-11-17
10838733 Register context restoration based on rename register recovery Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum 2020-11-17
10831476 Compare and delay instructions Charles W. Gainey, Jr., Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt 2020-11-10
10831480 Move data and set storage key instruction Elpida Tzortzatos 2020-11-10
10831497 Compression/decompression instruction specifying a history buffer to be used in the compression/decompression of data Bruce C. Giamei, Anthony T. Sofia, Matthias Klein, Simon Weishaupt, Mark S. Farrell +2 more 2020-11-10
10831478 Sort and merge instruction for a general-purpose processor Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Aditya N. Puranik, Mark S. Farrell +3 more 2020-11-10