Issued Patents All Time
Showing 101–125 of 347 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10170302 | Superlattice lateral bipolar junction transistor | Karthik Balakrishnan, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek | 2019-01-01 |
| 10170660 | Digital alloy germanium heterojunction solar cell | Karthik Balakrishnan, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek | 2019-01-01 |
| 10134831 | Deformable and flexible capacitor | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-11-20 |
| 10127649 | Electron channeling pattern acquisition from small crystalline areas | Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser | 2018-11-13 |
| 10115711 | Vertical light emitting diode with magnetic back contact | Bing Dang, Ning Li, Frank R. Libsch, Devendra K. Sadana | 2018-10-30 |
| 10083850 | Method of forming a flexible semiconductor layer and devices on a flexible carrier | Devendra K. Sadana, Katherine L. Saenger, Abdelmajid Salhi | 2018-09-25 |
| 10079341 | Three-terminal non-volatile multi-state memory for cognitive computing applications | Kevin W. Brew, Joel P. de Souza, Seyoung Kim, Ning Li, Yun Seog Lee +1 more | 2018-09-18 |
| 10074720 | Digital alloy vertical lamellae finfet with current flow in alloy layer direction | Karthik Balakrishnan, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek | 2018-09-11 |
| 10032973 | Magnetically guided chiplet displacement | Bing Dang, Ning Li, Frank R. Libsch, Devendra K. Sadana | 2018-07-24 |
| 10026618 | Method for improving quality of spalled material layers | Keith E. Fogel, Paul A. Lauro, Ning Li, Devendra K. Sadana, Katherine L. Saenger +1 more | 2018-07-17 |
| 10020418 | Simplified process for vertical LED manufacturing | Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana | 2018-07-10 |
| 10002856 | Micro-LED array transfer | Bing Dang, Ning Li, Frank R. Libsch, Devendra K. Sadana | 2018-06-19 |
| 9991408 | Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface | Ning Li, Devendra K. Sadana, Ghavam G. Shahidi | 2018-06-05 |
| 9985164 | Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface | Ning Li, Devendra K. Sadana, Ghavam G. Shahidi | 2018-05-29 |
| 9984941 | Non-destructive, wafer scale method to evaluate defect density in heterogeneous epitaxial layers | John A. Ott | 2018-05-29 |
| 9984871 | Superlattice lateral bipolar junction transistor | Karthik Balakrishnan, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek | 2018-05-29 |
| 9958390 | On-chip molecule fluorescence detection | Yann Astier, Ning Li, Devendra K. Sadana, William T. Spratt, Chao Wang | 2018-05-01 |
| 9941355 | Co-integration of elastic and plastic relaxation on the same wafer | Nicolas Loubet, Devendra K. Sadana | 2018-04-10 |
| 9935230 | Type IV semiconductor based high voltage laterally stacked multijunction photovoltaic cell | Ning Li, Devendra K. Sadana, Ghavam G. Shahidi | 2018-04-03 |
| 9935223 | Monolithic integration of heterojunction solar cells | Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi | 2018-04-03 |
| 9935185 | Superlattice lateral bipolar junction transistor | Karthik Balakrishnan, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek | 2018-04-03 |
| 9929313 | Protective capping layer for spalled gallium nitride | Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana | 2018-03-27 |
| 9922866 | Enhancing robustness of SOI substrate containing a buried N+ silicon layer for CMOS processing | Stephan A. Cohen, Joel P. de Souza, Karen A. Nummy, Daniel J. Poindexter, Devendra K. Sadana | 2018-03-20 |
| 9918382 | Patterned metallization handle layer for controlled spalling | Turki bin Saud bin Mohammed Al-Saud, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana | 2018-03-13 |
| 9899274 | Low-cost SOI FinFET technology | Joel P. de Souza, Alexander Reznicek, Devendra K. Sadana, Dominic J. Schepis | 2018-02-20 |