PH

Pouya Hashemi

IBM: 550 patents #15 of 70,183Top 1%
Globalfoundries: 25 patents #110 of 4,424Top 3%
ET Elpis Technologies: 3 patents #8 of 121Top 7%
Samsung: 2 patents #37,631 of 75,807Top 50%
TE Tessera: 1 patents #207 of 271Top 80%
📍 Purchase, NY: #1 of 53 inventorsTop 2%
🗺 New York: #17 of 115,490 inventorsTop 1%
Overall (All Time): #268 of 4,157,543Top 1%
581
Patents All Time

Issued Patents All Time

Showing 351–375 of 581 patents

Patent #TitleCo-InventorsDate
9812530 High germanium content silicon germanium fins Karthik Balakrishnan, John Bruley, Ali Khakifirooz, John A. Ott, Alexander Reznicek 2017-11-07
9812357 Self-limiting silicide in highly scaled fin technology Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek 2017-11-07
9806173 Channel-last replacement metal-gate vertical field effect transistor Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2017-10-31
9799777 Floating gate memory in a channel last vertical FET flow Karthik Balakrishnan, Tak H. Ning, Alexander Reznicek 2017-10-24
9799600 Nickel-silicon fuse for FinFET structures Kangguo Cheng, Keith E. Fogel, Alexander Reznicek 2017-10-24
9799569 Method of forming field effect transistors (FETs) with abrupt junctions and integrated circuit chips with the FETs Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek 2017-10-24
9799568 Field effect transistor including strained germanium fins Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2017-10-24
9793401 Vertical field effect transistor including extension and stressors Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2017-10-17
9793263 Digital alloy FinFET co-integrated with passive resistor with good temperature coefficient Karthik Balakrishnan, Stephen W. Bedell, Bahman Hekmatshoartabari, Alexander Reznicek 2017-10-17
9793113 Semiconductor structure having insulator pillars and semiconductor material on substrate Alexander Reznicek, Dominic J. Schepis, Kangguo Cheng, Bruce B. Doris 2017-10-17
9786782 Source/drain FinFET channel stressor structure Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2017-10-10
9786768 III-V vertical field effect transistors with tunable bandgap source/drain regions Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2017-10-10
9786758 Vertical Schottky barrier FET Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2017-10-10
9786739 Stacked nanosheets by aspect ratio trapping Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2017-10-10
9780194 Vertical transistor structure with reduced parasitic gate capacitance Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2017-10-03
9780173 High aspect ratio trapping semiconductor with uniform height and isolated from bulk substrate Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek 2017-10-03
9780100 Vertical floating gate memory with variable channel doping profile Karthik Balakrishnan, Tak H. Ning, Alexander Reznicek 2017-10-03
9780088 Co-fabrication of vertical diodes and fin field effect transistors on the same substrate Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2017-10-03
9779995 Highly scaled tunnel FET with tight pitch and method to fabricate same Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2017-10-03
9773913 Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2017-09-26
9773907 Method to controllably etch silicon recess for ultra shallow junctions Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek 2017-09-26
9773905 Strained FinFET by epitaxial stressor independent of gate pitch Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan V. Surisetty 2017-09-26
9773812 Integrated circuit with heterogeneous CMOS integration of strained silicon germanium and group III-V semiconductor materials and method to fabricate same Cheng-Wei Cheng, Effendi Leobandung, Alexander Reznicek 2017-09-26
9773780 Devices including gates with multiple lengths Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2017-09-26
9768272 Replacement gate FinFET process using a sit process to define source/drain regions, gate spacers and a gate cavity Hong He, Alexander Reznicek, Tenko Yamashita 2017-09-19