Issued Patents All Time
Showing 301–325 of 581 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9947689 | Semiconductor device structure with 110-PFET and 111-NFET current flow direction | Ali Khakifirooz, Shogo Mochizuki, Alexander Reznicek | 2018-04-17 |
| 9947675 | Mask-programmable ROM using a vertical FET integration process | Karthik Balakrishnan, Tak H. Ning, Alexander Reznicek | 2018-04-17 |
| 9947649 | Large area electrostatic dischage for vertical transistor structures | Karthik Balakrishnan, Alexander Reznicek, Jeng-Bang Yau | 2018-04-17 |
| 9941370 | Vertical field-effect-transistors having multiple threshold voltages | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2018-04-10 |
| 9935186 | Method of manufacturing SOI lateral Si-emitter SiGe base HBT | Tak H. Ning, Alexander Reznicek | 2018-04-03 |
| 9935185 | Superlattice lateral bipolar junction transistor | Karthik Balakrishnan, Stephen W. Bedell, Bahman Hekmatshoartabari, Alexander Reznicek | 2018-04-03 |
| 9929270 | Gate all-around FinFET device and a method of manufacturing same | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2018-03-27 |
| 9929266 | Method and structure for incorporating strain in nanosheet devices | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2018-03-27 |
| 9929258 | Method of junction control for lateral bipolar junction transistor | Kam-Leung Lee, Tak H. Ning, Jeng-Bang Yau | 2018-03-27 |
| 9923084 | Forming a fin using double trench epitaxy | Veeraraghavan S. Basker, Shogo Mochizuki, Alexander Reznicek | 2018-03-20 |
| 9922886 | Silicon-germanium FinFET device with controlled junction | Kangguo Cheng, Kam-Leung Lee, Alexander Reznicek | 2018-03-20 |
| 9917200 | Nanowire transistor structures with merged source/drain regions using auxiliary pillars | Ali Khakifirooz, Alexander Reznicek | 2018-03-13 |
| 9917179 | Stacked nanowire devices formed using lateral aspect ratio trapping | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2018-03-13 |
| 9917175 | Tapered vertical FET having III-V channel | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2018-03-13 |
| 9917015 | Dual channel material for finFET for high performance CMOS | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2018-03-13 |
| 9911662 | Forming a CMOS with dual strained channels | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2018-03-06 |
| 9911741 | Dual channel material for finFET for high performance CMOS | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2018-03-06 |
| 9905649 | Tensile strained nFET and compressively strained pFET formed on strain relaxed buffer | Karthik Balakrishnan, Keith E. Fogel, Alexander Reznicek | 2018-02-27 |
| 9899495 | Vertical transistors with reduced bottom electrode series resistance | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2018-02-20 |
| 9893014 | Designable channel FinFET fuse | Keith E. Fogel, Shogo Mochizuki, Alexander Reznicek | 2018-02-13 |
| 9893151 | Method and apparatus providing improved thermal conductivity of strain relaxed buffer | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2018-02-13 |
| 9893207 | Programmable read only memory (ROM) integrated in tight pitch vertical transistor structures | Karthik Balakrishnan, Tak H. Ning, Alexander Reznicek | 2018-02-13 |
| 9892925 | Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy | Kangguo Cheng, Shogo Mochizuki, Alexander Reznicek | 2018-02-13 |
| 9892975 | Adjacent strained <100> NFET fins and <110> PFET fins | Kangguo Cheng, Bruce B. Doris, Alexander Reznicek | 2018-02-13 |
| 9892978 | Forming a CMOS with dual strained channels | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2018-02-13 |