Issued Patents All Time
Showing 76–100 of 151 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9189051 | Power reduction by minimizing bit transitions in the hamming distances of encoded communications | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2015-11-17 |
| 9183399 | Instruction set architecture with secure clear instructions for protecting processing unit architected state information | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2015-11-10 |
| 9176885 | Combined cache inject and lock operation | Jamie R. Kuesel, Mark G. Kupferschmidt, Robert A. Shearer | 2015-11-03 |
| 9170954 | Translation management instructions for updating address translation data structures in remote processing nodes | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2015-10-27 |
| 9147078 | Instruction set architecture with secure clear instructions for protecting processing unit architected state information | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2015-09-29 |
| 9134778 | Power distribution management in a system on a chip | Jamie R. Kuesel, Mark G. Kupferschmidt, Robert A. Shearer | 2015-09-15 |
| 9134779 | Power distribution management in a system on a chip | Jamie R. Kuesel, Mark G. Kupferschmidt, Robert A. Shearer | 2015-09-15 |
| 9122465 | Programmable microcode unit for mapping plural instances of an instruction in plural concurrently executed instruction streams to plural microcode sequences in plural memory partitions | Robert A. Shearer, Matthew R. Tubbs | 2015-09-01 |
| 9092256 | Vector execution unit with prenormalization of denormal values | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2015-07-28 |
| 9092257 | Vector execution unit with prenormalization of denormal values | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2015-07-28 |
| 9075623 | External auxiliary execution unit interface for format conversion of instruction from issue unit to off-chip auxiliary execution unit | Eric O. Mejdrich, Robert A. Shearer, Corey V. Swenson | 2015-07-07 |
| 9053049 | Translation management instructions for updating address translation data structures in remote processing nodes | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2015-06-09 |
| 9043801 | Two-tiered dynamic load balancing using sets of distributed thread pools | Mark G. Kupferschmidt, Robert A. Shearer | 2015-05-26 |
| 9032191 | Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2015-05-12 |
| 8990833 | Indirect inter-thread communication using a shared pool of inboxes | Jamie R. Kuesel, Mark G. Kupferschmidt, Robert A. Shearer | 2015-03-24 |
| 8984260 | Predecode logic autovectorizing a group of scalar instructions including result summing add instruction to a vector instruction for execution in vector unit with dot product adder | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2015-03-17 |
| 8954755 | Memory address translation-based data encryption with integrated encryption engine | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2015-02-10 |
| 8935694 | System and method for selectively saving and restoring state of branch prediction logic through separate hypervisor-mode and guest-mode and/or user-mode instructions | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2015-01-13 |
| 8898396 | Software pipelining on a network on chip | Eric O. Mejdrich, Robert A. Shearer | 2014-11-25 |
| 8892851 | Changing opcode of subsequent instruction when same destination address is not used as source address by intervening instructions | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2014-11-18 |
| 8836709 | Vector register file caching of context data structure for maintaining state data in a multithreaded image processing pipeline | Eric O. Mejdrich, Robert A. Shearer, Matthew R. Tubbs | 2014-09-16 |
| 8826299 | Spawned message state determination | Jon K. Kriegel, Mark G. Kupferschmidt | 2014-09-02 |
| 8776035 | Providing performance tuned versions of compiled code to a CPU in a system of heterogeneous cores | Jamie R. Kuesel, Mark G. Kupferschmidt, Robert A. Shearer | 2014-07-08 |
| 8773449 | Rendering of stereoscopic images with multithreaded rendering software pipeline | Russell D. Hoover, Eric O. Mejdrich, Robert A. Shearer | 2014-07-08 |
| 8751830 | Memory address translation-based data encryption/compression | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2014-06-10 |