Issued Patents All Time
Showing 51–75 of 151 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9542184 | Local instruction loop buffer utilizing execution unit register file | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2017-01-10 |
| 9507599 | Instruction set architecture with extensible register addressing | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-11-29 |
| 9501279 | Local instruction loop buffer utilizing execution unit register file | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-11-22 |
| 9465613 | Instruction predication using unused datapath facilities | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-10-11 |
| 9405536 | Floating point execution unit for calculating packed sum of absolute differences | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-08-02 |
| 9405535 | Floating point execution unit for calculating packed sum of absolute differences | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-08-02 |
| 9354887 | Instruction buffer bypass of target instruction in response to partial flush | Eric O. Mejdrich, Robert A. Shearer, Matthew R. Tubbs | 2016-05-31 |
| 9342309 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-05-17 |
| 9329870 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-05-03 |
| 9317294 | Concurrent multiple instruction issue of non-pipelined instructions using non-pipelined operation resources in another processing core | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-04-19 |
| 9317291 | Local instruction loop buffer utilizing execution unit register file | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-04-19 |
| 9311096 | Local instruction loop buffer utilizing execution unit register file | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-04-12 |
| 9311090 | Indirect instruction predication | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-04-12 |
| 9304771 | Indirect instruction predication | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-04-05 |
| 9292965 | Accelerated data structure positioning based upon view orientation | David Keith Fowler, Eric O. Mejdrich, Robert A. Shearer | 2016-03-22 |
| 9292290 | Instruction set architecture with opcode lookup using memory attribute | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-03-22 |
| 9286071 | Instruction set architecture with opcode lookup using memory attribute | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-03-15 |
| 9274591 | General purpose processing unit with low power digital signal processing (DSP) mode | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-03-01 |
| 9256574 | Dynamic thread status retrieval using inter-thread communication | Jamie R. Kuesel, Mark G. Kupferschmidt, Robert A. Shearer | 2016-02-09 |
| 9256573 | Dynamic thread status retrieval using inter-thread communication | Jamie R. Kuesel, Mark G. Kupferschmidt, Robert A. Shearer | 2016-02-09 |
| 9251116 | Direct interthread communication dataport pack/unpack and load/save | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2016-02-02 |
| 9244840 | Cache swizzle with inline transposition | Jamie R. Kuesel, Mark G. Kupferschmidt, Robert A. Shearer | 2016-01-26 |
| 9239791 | Cache swizzle with inline transposition | Jamie R. Kuesel, Mark G. Kupferschmidt, Robert A. Shearer | 2016-01-19 |
| 9218039 | Chip level power reduction using encoded communications | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2015-12-22 |
| 9195443 | Providing performance tuned versions of compiled code to a CPU in a system of heterogeneous cores | Jamie R. Kuesel, Mark G. Kupferschmidt, Robert A. Shearer | 2015-11-24 |