Issued Patents All Time
Showing 26–50 of 151 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10656855 | Memory management in a programmable device | Jim C. Chen, Lance G. Thompson, James E. Carey | 2020-05-19 |
| 10599553 | Managing cloud-based hardware accelerators | Jim C. Chen, Lance G. Thompson, James E. Carey | 2020-03-24 |
| 10572250 | Dynamic accelerator generation and deployment | James E. Carey, Jim C. Chen, Lance G. Thompson | 2020-02-25 |
| 10545797 | Dynamic thread status retrieval using inter-thread communication | Jamie R. Kuesel, Mark G. Kupferschmidt, Robert A. Shearer | 2020-01-28 |
| 10534654 | Dynamic thread status retrieval using inter-thread communication | Jamie R. Kuesel, Mark G. Kupferschmidt, Robert A. Shearer | 2020-01-14 |
| 10521234 | Concurrent multiple instruction issued of non-pipelined instructions using non-pipelined operation resources in another processing core | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2019-12-31 |
| 10496586 | Accelerator management | Jim C. Chen, Lance G. Thompson, James E. Carey | 2019-12-03 |
| 9911212 | Resetting of dynamically grown accelerated data structure | David Keith Fowler, Eric O. Mejdrich, Robert A. Shearer | 2018-03-06 |
| 9710274 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2017-07-18 |
| 9678885 | Regular expression memory region with integrated regular expression engine | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2017-06-13 |
| 9652238 | Instruction set architecture with opcode lookup using memory attribute | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2017-05-16 |
| 9652239 | Instruction set architecture with opcode lookup using memory attribute | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2017-05-16 |
| 9632786 | Instruction set architecture with extended register addressing using one or more primary opcode bits | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2017-04-25 |
| 9632779 | Instruction predication using instruction filtering | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2017-04-25 |
| 9619234 | Indirect instruction predication | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2017-04-11 |
| 9607120 | Implementing system irritator accelerator FPGA unit (AFU) residing behind a coherent attached processors interface (CAPI) unit | Jason Greenwood, Steven D. McJunkin, Nathaniel K. Tuen | 2017-03-28 |
| 9606950 | Verifying runtime switch-over between multiple I/O protocols on shared I/O connection | Thomas M. Armstead, John H. Klaus, Scott M. Willenborg | 2017-03-28 |
| 9606841 | Thread scheduling across heterogeneous processing elements with resource mapping | Jamie R. Kuesel, Mark G. Kupferschmidt, Robert A. Shearer | 2017-03-28 |
| 9600618 | Implementing system irritator accelerator FPGA unit (AFU) residing behind a coherent attached processors interface (CAPI) unit | Jason Greenwood, Steven D. McJunkin, Nathaniel K. Tuen | 2017-03-21 |
| 9600432 | Verifying runtime switch-over between multiple I/O protocols on shared I/O connection | Thomas M. Armstead, John H. Klaus, Scott M. Willenborg | 2017-03-21 |
| 9600346 | Thread scheduling across heterogeneous processing elements with resource mapping | Jamie R. Kuesel, Mark G. Kupferschmidt, Robert A. Shearer | 2017-03-21 |
| 9594562 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2017-03-14 |
| 9594557 | Floating point execution unit for calculating packed sum of absolute differences | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2017-03-14 |
| 9594556 | Floating point execution unit for calculating packed sum of absolute differences | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2017-03-14 |
| 9582277 | Indirect instruction predication | Adam J. Muff, Robert A. Shearer, Matthew R. Tubbs | 2017-02-28 |