Issued Patents All Time
Showing 376–400 of 836 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9916185 | Managing processing associated with selected architectural facilities | Charles W. Gainey, Jr. | 2018-03-13 |
| 9916180 | Interprocessor memory status communication | Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-03-13 |
| 9916179 | Interprocessor memory status communication | Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-03-13 |
| 9910781 | Page table including data fetch width indicator | Jose E. Moreira, Balaram Sinharoy | 2018-03-06 |
| 9910769 | Alignment based block concurrency for accessing memory | Jonathan D. Bradbury, Christian Jacobi, Timothy J. Slegel | 2018-03-06 |
| 9904618 | Alignment based block concurrency for accessing memory | Jonathan D. Bradbury, Christian Jacobi, Timothy J. Slegel | 2018-02-27 |
| 9904572 | Dynamic prediction of hardware transaction resource requirements | Fadi Y. Busaba, Dan F. Greiner, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2018-02-27 |
| 9898331 | Dynamic releasing of cache lines | Jonathan D. Bradbury, Chung-Lung K. Shum, Timothy J. Slegel | 2018-02-20 |
| 9898296 | Selective suppression of instruction translation lookaside buffer (ITLB) access | Valentina Salapura | 2018-02-20 |
| 9892052 | Hybrid tracking of transaction read and write sets | Valentina Salapura, Chung-Lung K. Shum | 2018-02-13 |
| 9891919 | Caller protected stack return address in a hardware managed stack architecture | Karl J. Duvalsaint, Valentina Salapura | 2018-02-13 |
| 9886252 | Compiler optimizations for vector operations that are reformatting-resistant | William J. Schmidt | 2018-02-06 |
| 9880835 | Initialization status of a register employed as a pointer | — | 2018-01-30 |
| 9880833 | Initialization status of a register employed as a pointer | — | 2018-01-30 |
| 9880821 | Compiler optimizations for vector operations that are reformatting-resistant | William J. Schmidt | 2018-01-30 |
| 9875082 | Single operation array index computation | — | 2018-01-23 |
| 9870308 | Debugging of prefixed code | — | 2018-01-16 |
| 9870305 | Debugging of prefixed code | — | 2018-01-16 |
| 9870254 | Multithreaded transactions | Fadi Y. Busaba, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2018-01-16 |
| 9870253 | Enabling end of transaction detection using speculative look ahead | Maged M. Michael, Valentina Salapura | 2018-01-16 |
| 9870210 | Partition mobility for partitions with extended code | Valentina Salapura | 2018-01-16 |
| 9864692 | Managing read tags in a transactional memory | Dan F. Greiner, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-01-09 |
| 9864690 | Detecting cache conflicts by utilizing logical address comparisons in a transactional memory | Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-01-09 |
| 9864518 | Assigning home memory addresses to function call parameters | Ulrich Weigand | 2018-01-09 |
| 9858074 | Non-default instruction handling within transaction | Jonathan D. Bradbury, Maged M. Michael, Eric M. Schwarz, Valentina Salapura, Chung-Lung K. Shum | 2018-01-02 |