Issued Patents All Time
Showing 326–350 of 836 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10073784 | Memory performance when speculation control is enabled, and instruction therefor | — | 2018-09-11 |
| 10073770 | Scheme for determining data object usage in a memory region | Giles R. Frazier, Younes Manton, Karl M. Taylor, Brian W. Thompto | 2018-09-11 |
| 10067716 | Inaccessibility status indicator | Brett Olsson | 2018-09-04 |
| 10061705 | Identifying instructions for decode-time instruction optimization grouping in view of cache boundaries | Valentina Salapura | 2018-08-28 |
| 10061703 | Prefetch insensitive transactional memory | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2018-08-28 |
| 10061588 | Tracking operand liveness information in a computer system and performing function based on the liveness information | Valentina Salapura | 2018-08-28 |
| 10061586 | Latent modification instruction for transactional execution | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2018-08-28 |
| 10061580 | Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence | — | 2018-08-28 |
| 10061572 | Reconfiguration of address space based on loading short pointer mode application | — | 2018-08-28 |
| 10061539 | Inaccessibility status indicator | Brett Olsson | 2018-08-28 |
| 10055348 | Transactional execution in a multi-processor environment that monitors memory conflicts in a shared cache | Fadi Y. Busaba, Eric M. Schwarz, Chung-Lung K. Shum | 2018-08-21 |
| 10055230 | Accurate tracking of transactional read and write sets with speculation | Valentina Salapura, Chung-Lung K. Shum | 2018-08-21 |
| 10042765 | Read and write sets for transactions of a multithreaded computing environment | Valentina Salapura | 2018-08-07 |
| 10042761 | Read and write sets for transactions of a multithreaded computing environment | Valentina Salapura | 2018-08-07 |
| 10042749 | Prefetch insensitive transactional memory | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2018-08-07 |
| 10025715 | Conditional inclusion of data in a transactional memory read set | Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-07-17 |
| 10019357 | Supporting atomic accumulation with an addressable accumulator | Fadi Y. Busaba, Eric M. Schwarz | 2018-07-10 |
| 10013351 | Transactional execution processor having a co-processor accelerator, both sharing a higher level cache | Fadi Y. Busaba, Eric M. Schwarz, Chung-Lung K. Shum | 2018-07-03 |
| 10013270 | Application-level initiation of processor parameter adjustment | Giles R. Frazier | 2018-07-03 |
| 10013258 | Single instruction array index computation | — | 2018-07-03 |
| 9997050 | Tracking a user based on an electronic noise profile | Valentina Salapura | 2018-06-12 |
| 9996326 | Layered vector architecture compatibility for cross-system portability | Ronald I. McIntosh | 2018-06-12 |
| 9983904 | Multithreaded transactions | Fadi Y. Busaba, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2018-05-29 |
| 9971713 | Multi-petascale highly efficient parallel supercomputer | Sameh W. Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle +54 more | 2018-05-15 |
| 9971690 | Transactional memory operations with write-only atomicity | Chung-Lung K. Shum, Timothy J. Slegel | 2018-05-15 |