Issued Patents All Time
Showing 276–300 of 836 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10180921 | Non-interfering transactions | Valentina Salapura | 2019-01-15 |
| 10180910 | Host-based resetting of active use of guest page table indicators | Jonathan D. Bradbury | 2019-01-15 |
| 10180909 | Host-based resetting of active use of guest page table indicators | Jonathan D. Bradbury | 2019-01-15 |
| 10180902 | Pauseless location and object handle based garbage collection | Giles R. Frazier | 2019-01-15 |
| 10180827 | Suppressing storing of context information | — | 2019-01-15 |
| 10176111 | Host page management using active guest page table indicators | Jonathan D. Bradbury, Lisa C. Heller, Christian Jacobi, Damian L. Osisek, Anthony Saporito | 2019-01-08 |
| 10176110 | Marking storage keys to indicate memory used to back address translation structures | Jonathan D. Bradbury | 2019-01-08 |
| 10176093 | Pauseless location and object handle based garbage collection | Giles R. Frazier | 2019-01-08 |
| 10175966 | Linker rewriting to eliminate TOC pointer references | Ulrich Weigand | 2019-01-08 |
| 10169267 | Transactional execution enabled supervisor call interruption while in TX mode | Jonathan D. Bradbury, Dan F. Greiner, Chung-Lung K. Shum | 2019-01-01 |
| 10169239 | Managing a prefetch queue based on priority indications of prefetch requests | Dan F. Greiner, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2019-01-01 |
| 10169228 | Multi-section garbage collection | Giles R. Frazier, Younes Manton, Karl M. Taylor, Brian W. Thompto | 2019-01-01 |
| 10169016 | Executing optimized local entry points | Ulrich Weigand | 2019-01-01 |
| 10169014 | Compiler method for generating instructions for vector operations in a multi-endian instruction set | Jin Song Ji, Ronald I. McIntosh, William J. Schmidt | 2019-01-01 |
| 10169012 | Compiler optimizations for vector operations that are reformatting-resistant | William J. Schmidt | 2019-01-01 |
| 10168961 | Hardware transaction transient conflict resolution | Jonathan D. Bradbury, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum +1 more | 2019-01-01 |
| 10169011 | Comparisons in function pointer localization | Ulrich Weigand | 2019-01-01 |
| 10162764 | Marking page table/page status table entries to indicate memory used to back address translation structures | Jonathan D. Bradbury | 2018-12-25 |
| 10162635 | Confidence-driven selective predication of processor instructions | — | 2018-12-25 |
| 10162660 | Application-level processor parameter management | Giles R. Frazier | 2018-12-25 |
| 10162743 | Prefetch insensitive transactional memory | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2018-12-25 |
| 10162744 | Prefetch insensitive transactional memory | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2018-12-25 |
| 10157131 | Transactional execution processor having a co-processor accelerator, both sharing a higher level cache | Fadi Y. Busaba, Eric M. Schwarz, Chung-Lung K. Shum | 2018-12-18 |
| 10157119 | Configurable code fingerprint | Giles R. Frazier, Christian Jacobi, Chung-Lung K. Shum | 2018-12-18 |
| 10152324 | Virtualization in a bi-endian-mode processor architecture | Brett Olsson | 2018-12-11 |