Issued Patents All Time
Showing 351–375 of 836 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9971629 | Dynamic releasing of cache lines | Jonathan D. Bradbury, Chung-Lung K. Shum, Timothy J. Slegel | 2018-05-15 |
| 9971628 | Salvaging hardware transactions | Harold W. Cain, III, Maged M. Michael, Valentina Salapura, Eric M. Schwarz | 2018-05-15 |
| 9971626 | Coherence protocol augmentation to indicate transaction status | Fadi Y. Busaba, Harold W. Cain, III, Christian Jacobi, Valentina Salapura, Eric M. Schwarz +1 more | 2018-05-15 |
| 9959118 | Instruction to load data up to a dynamically determined memory boundary | Jonathan D. Bradbury, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel | 2018-05-01 |
| 9959117 | Instruction to load data up to a specified memory boundary indicated by the instruction | Jonathan D. Bradbury, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel | 2018-05-01 |
| 9959102 | Layered vector architecture compatibility for cross-system portability | Ronald I. McIntosh | 2018-05-01 |
| 9952976 | Allowing non-cacheable loads within a transaction | Jonathan D. Bradbury, Valentina Salapura, Chung-Lung K. Shum | 2018-04-24 |
| 9952943 | Salvaging hardware transactions | Harold W. Cain, III, Maged M. Michael, Valentina Salapura, Eric M. Schwarz | 2018-04-24 |
| 9952884 | Executing optimized local entry points and function call sites | Ulrich Weigand | 2018-04-24 |
| 9952862 | Instruction to load data up to a dynamically determined memory boundary | Jonathan D. Bradbury, Christian Jacobi, Eric M. Schwartz, Timothy J. Slegel | 2018-04-24 |
| 9952844 | Executing optimized local entry points and function call sites | Ulrich Weigand | 2018-04-24 |
| 9952804 | Hardware transaction transient conflict resolution | Jonathan D. Bradbury, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum +1 more | 2018-04-24 |
| 9946542 | Instruction to load data up to a specified memory boundary indicated by the instruction | Jonathan D. Bradbury, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel | 2018-04-17 |
| 9946521 | Programmable code fingerprint | Giles R. Frazier, Christian Jacobi, Chung-Lung K. Shum | 2018-04-17 |
| 9946494 | Hardware transaction transient conflict resolution | Jonathan D. Bradbury, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum +1 more | 2018-04-17 |
| 9940475 | Interlinking routines with differing protections using stack indicators | — | 2018-04-10 |
| 9940242 | Techniques for identifying instructions for decode-time instruction optimization grouping in view of cache boundaries | Valentina Salapura | 2018-04-10 |
| 9940135 | Instruction stream modification for memory transaction protection | Fadi Y. Busaba, Maged M. Michael, Chung-Lung K. Shum, Valentina Salapura, Timothy J. Slegel | 2018-04-10 |
| 9928173 | Conditional inclusion of data in a transactional memory read set | Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-03-27 |
| 9928064 | Instruction stream modification for memory transaction protection | Fadi Y. Busaba, Maged M. Michael, Chung-Lung K. Shum, Valentina Salapura, Timothy J. Slegel | 2018-03-27 |
| 9921895 | Transactional memory operations with read-only atomicity | Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-03-20 |
| 9921843 | Predictive fetching and decoding for selected instructions | Valentina Salapura | 2018-03-20 |
| 9921834 | Prefetching of discontiguous storage locations in anticipation of transactional execution | Fadi Y. Busaba, Dan F. Greiner, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2018-03-20 |
| 9916239 | Multi-section garbage collection | Giles R. Frazier, Younes Manton, Karl M. Taylor, Brian W. Thompto | 2018-03-13 |
| 9916186 | Managing processing associated with selected architectural facilities | Charles W. Gainey, Jr. | 2018-03-13 |