Issued Patents All Time
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10108423 | History buffer with single snoop tag for multiple-field registers | Dung Q. Nguyen, Kenneth L. Ward | 2018-10-23 |
| 10067766 | History buffer with hybrid entry support for multiple-field registers | Dung Q. Nguyen | 2018-09-04 |
| 9996353 | Universal history buffer to support multiple register types | Hung Q. Le, Dung Q. Nguyen, Kenneth L. Ward | 2018-06-12 |
| 9971604 | History buffer for multiple-field registers | Sundeep Chadha, Dung Q. Nguyen, David R. Terry, Kenneth L. Ward | 2018-05-15 |
| 9959123 | Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor | Joshua W. Bowman, Sundeep Chadha, Dhivya Jeganathan, Dung Q. Nguyen, David R. Terry +1 more | 2018-05-01 |
| 9952874 | Operation of a multi-slice processor with selective producer instruction types | Brian D. Barrick, Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Rokesh Jayasundar +2 more | 2018-04-24 |
| 9952861 | Operation of a multi-slice processor with selective producer instruction types | Brian D. Barrick, Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Rokesh Jayasundar +2 more | 2018-04-24 |
| 9928073 | Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor | Joshua W. Bowman, Sundeep Chadha, Dhivya Jeganathan, Dung Q. Nguyen, David R. Terry +1 more | 2018-03-27 |
| 9921833 | Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor | Joshua W. Bowman, Sundeep Chadha, Dhivya Jeganathan, Dung Q. Nguyen, David R. Terry +1 more | 2018-03-20 |
| 9858078 | Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor | Joshua W. Bowman, Sundeep Chadha, Dhivya Jeganathan, Dung Q. Nguyen, David R. Terry +1 more | 2018-01-02 |
| 9747217 | Distributed history buffer flush and restore handling in a parallel slice design | Salma Ayub, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen, David R. Terry | 2017-08-29 |
| 9740620 | Distributed history buffer flush and restore handling in a parallel slice design | Salma Ayub, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen, David R. Terry | 2017-08-22 |
| 9110708 | Region-weighted accounting of multi-threaded processor core according to dispatch state | James Wilson Bishop, Steven B. Herndon, Philip L. Vitale | 2015-08-18 |
| 9015449 | Region-weighted accounting of multi-threaded processor core according to dispatch state | James Wilson Bishop, Steven B. Herndon, Philip L. Vitale | 2015-04-21 |
| 8230440 | System and method to distribute accumulated processor utilization charges among multiple threads | Rolf Hilgendorf | 2012-07-24 |
| 7844849 | System and method for identifying and manipulating logic analyzer data from multiple clock domains | John Fred Spannaus | 2010-11-30 |