Issued Patents All Time
Showing 76–100 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7764533 | Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition | Chung H. Lam, Bipin Rajendran | 2010-07-27 |
| 7700446 | Virtual body-contacted trigate | Brent A. Anderson, Edward J. Nowak, BethAnn Rainey | 2010-04-20 |
| 7691684 | Fin-type antifuse | Chung H. Lam, Edward J. Nowak | 2010-04-06 |
| 7682945 | Phase change element extension embedded in an electrode | Chung H. Lam, Roger W. Cheek, Alejandro G. Schrott, Matthew D. Moon | 2010-03-23 |
| 7602632 | Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition | Chung H. Lam, Bipin Rajendran | 2009-10-13 |
| 7602631 | Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition | Chung H. Lam, Bipin Rajendran | 2009-10-13 |
| 7567473 | Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition | Chung H. Lam, Bipin Rajendran | 2009-07-28 |
| 7560721 | Phase change material with filament electrode | Roger W. Cheek, Eric A. Joseph, Chung H. Lam, Alejandro G. Schrott, Gerhard Ingmar Meijer | 2009-07-14 |
| 7551473 | Programmable resistive memory with diode structure | Hsiang-Lan Lung, Chung H. Lam | 2009-06-23 |
| 7525176 | Phase change memory cell design with adjusted seam location | Thomas Happ, Alejandro G. Schrott | 2009-04-28 |
| 7514705 | Phase change memory cell with limited switchable volume | Chung H. Lam, Jan Boris Philipp, Stephen M. Rossnagel, Alejandro G. Schrott | 2009-04-07 |
| 7505334 | Measurement method for reading multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition | Chung H. Lam, Bipin Rajendran | 2009-03-17 |
| 7485487 | Phase change memory cell with electrode | Roger W. Cheek, Eric A. Joseph, Chung H. Lam, Alejandro G. Schrott | 2009-02-03 |
| 7479671 | Thin film phase change memory cell formed on silicon-on-insulator substrate | Chung H. Lam, Alejandro G. Schrott | 2009-01-20 |
| 7426134 | Sense circuit for resistive memory | Thomas Happ, Hsiang-Lang Lung | 2008-09-16 |
| 7411252 | Substrate backgate for trigate FET | Brent A. Anderson, Edward J. Nowak | 2008-08-12 |
| 7378710 | FinFET SRAM cell using inverted FinFET thin film transistors | Edward J. Nowak | 2008-05-27 |
| 7288802 | Virtual body-contacted trigate | Brent A. Anderson, Edward J. Nowak, BethAnn Rainey | 2007-10-30 |
| 7190007 | Isolated fully depleted silicon-on-insulator regions by selective etch | Chung H. Lam, Randy W. Mann, Dale W. Martin | 2007-03-13 |
| 7123517 | Reprogrammable integrated circuit (IC) with overwritable nonvolatile storage | Chung H. Lam, Steven W. Mittl, Jian Zhu | 2006-10-17 |
| 6967380 | CMOS device having retrograde n-well and p-well | Chung H. Lam, James A. Slinkman | 2005-11-22 |
| 6881672 | Selective silicide blocking | Jeffrey S. Brown, Terence B. Hook, Randy W. Mann, Christopher S. Putnam, Mohammad I. Younus | 2005-04-19 |
| 6778449 | Method and design for measuring SRAM array leakage macro (ALM) | Jeffrey S. Brown, Randy W. Mann, Jeffrey H. Oppold | 2004-08-17 |
| 6700163 | Selective silicide blocking | Jeffrey S. Brown, Terence B. Hook, Randy W. Mann, Christopher S. Putnam, Mohammad I. Younus | 2004-03-02 |
| 6667205 | Method of forming retrograde n-well and p-well | Chung H. Lam, James A. Slinkman | 2003-12-23 |