Issued Patents All Time
Showing 51–73 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11251280 | Strained nanowire transistor with embedded epi | Heng Wu, Chen Zhang, Kangguo Cheng, Xin Miao | 2022-02-15 |
| 11239119 | Replacement bottom spacer for vertical transport field effect transistors | Ruilong Xie, Heng Wu, Jay William Strane, Hemanth Jagannathan, Tao Li | 2022-02-01 |
| 11189725 | VTFET with cell height constraints | Heng Wu, Ruilong Xie, Alexander Reznicek, Junli Wang | 2021-11-30 |
| 11189713 | Nanosheet transistor having wrap-around bottom isolation | Ruilong Xie, Heng Wu, Kangguo Cheng | 2021-11-30 |
| 11177258 | Stacked nanosheet CFET with gate all around structure | Ruilong Xie, Alexander Reznicek, Heng Wu | 2021-11-16 |
| 11177369 | Stacked vertical field effect transistor with self-aligned junctions | Xin Miao, Chen Zhang, Heng Wu, Kangguo Cheng | 2021-11-16 |
| 11164870 | Stacked upper fin and lower fin transistor with separate gate | Heng Wu, Ruilong Xie, Chun Wing Yeung | 2021-11-02 |
| 11164947 | Wrap around contact formation for VTFET | Heng Wu, Ruilong Xie, Shogo Mochizuki | 2021-11-02 |
| 11094798 | Vertical FET with symmetric junctions | Xin Miao, Chen Zhang, Heng Wu, Kangguo Cheng | 2021-08-17 |
| 11075334 | Spin-orbit-torque magneto-resistive random access memory with stepped bottom electrode | Alexander Reznicek, Ruilong Xie, Heng Wu | 2021-07-27 |
| 11056588 | Vertical transport field effect transistor with bottom source/drain | Heng Wu, Gen Tsutsui, Ruilong Xie | 2021-07-06 |
| 11024369 | Static random-access memory cell design | Junli Wang, Heng Wu, Ruqiang Bao, Dechao Guo | 2021-06-01 |
| 11024670 | Forming an MRAM device over a transistor | Alexander Reznicek, Ruilong Xie, Heng Wu | 2021-06-01 |
| 11011517 | Semiconductor structure including first FinFET devices for low power applications and second FinFET devices for high power applications | Junli Wang, Heng Wu, Ruqiang Bao, Dechao Guo | 2021-05-18 |
| 11004984 | Low resistivity epitaxially formed contact region for nanosheet external resistance reduction | Heng Wu, Oleg Gluschenkov, Ruilong Xie | 2021-05-11 |
| 10943989 | Gate to source/drain leakage reduction in nanosheet transistors via inner spacer optimization | Heng Wu, Ruqiang Bao, Junli Wang, Dechao Guo | 2021-03-09 |
| 10910470 | Nanosheet transistors with inner airgaps | Heng Wu, Ruilong Xie, Alexander Reznicek | 2021-02-02 |
| 10868033 | Three-dimensional memory devices and fabricating methods thereof | Lei Ding, Jing Gao, Chuan Yang, Ping Yan, Sen Zhang +1 more | 2020-12-15 |
| 10833198 | Confined source drain epitaxy to reduce shorts in CMOS integrated circuits | Ruilong Xie, Chun-Chen Yeh, Alexander Reznicek | 2020-11-10 |
| 10797163 | Leakage control for gate-all-around field-effect transistor devices | Heng Wu, Ruqiang Bao, Junli Wang, Dechao Guo | 2020-10-06 |
| 10640003 | Double-pulse test systems and methods | Xi Lu, Chingchi Chen, Zhuxian Xu, Krishna Prasad Bhat, Michael W. Degner | 2020-05-05 |
| 10527653 | Ultra-high bandwidth current shunt | Richard William Kautz, Xi Lu, Zhuxian Xu, Guangyin Lei, Chingchi Chen +1 more | 2020-01-07 |
| 10239407 | Variable carrier switching frequency control of variable voltage converter | Michael W. Degner | 2019-03-26 |