Issued Patents All Time
Showing 2,751–2,775 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7569434 | PFETs and methods of manufacturing the same | Louis L. Hsu, Jack A. Mandelman, Haining Yang | 2009-08-04 |
| 7563670 | Method for etching single-crystal semiconductor selective to amorphous/polycrystalline semiconductor and structure formed by same | Richard O. Henry, Kenneth T. Settlemyer, Jr. | 2009-07-21 |
| 7560387 | Opening hard mask and SOI substrate in single process chamber | Scott D. Allen, Xi Li, Kevin R. Winstel | 2009-07-14 |
| 7560360 | Methods for enhancing trench capacitance and trench capacitor | David M. Dobuzinsky, Xi Li | 2009-07-14 |
| 7560761 | Semiconductor structure including trench capacitor and trench resistor | Robert M. Rassel | 2009-07-14 |
| 7560784 | Fin PIN diode | Louis L. Hsu, Jack A. Mandelman | 2009-07-14 |
| 7550359 | Methods involving silicon-on-insulator trench memory with implanted plate | Herbert L. Ho, Geng Wang | 2009-06-23 |
| 7550773 | FinFET with top body contact | Roger A. Booth, Jr., Jack A. Mandelman | 2009-06-23 |
| 7547608 | Polysilicon hard mask for enhanced alignment signal | Johnathan E. Faltermeier, James P. Norum | 2009-06-16 |
| 7531423 | Reduced-resistance finFETs by sidewall silicidation and methods of manufacturing the same | Louis L. Hsu, Jack A. Mandelman, Haining Yang | 2009-05-12 |
| 7528035 | Vertical trench memory cell with insulating ring | — | 2009-05-05 |
| 7525170 | Pillar P-i-n semiconductor diodes | Louis L. Hsu, Jack A. Mandelman | 2009-04-28 |
| 7497959 | Methods and structures for protecting one area while processing another area on a chip | Deok-kee Kim, Kenneth T. Settlemyer, Jr., Ramachandra Divakaruni, Carl Radens, Dirk Pfeiffer +4 more | 2009-03-03 |
| 7494891 | Trench capacitor with void-free conductor fill | Johnathan E. Faltermeier, Xi Li | 2009-02-24 |
| 7491604 | Trench memory with monolithic conducting material and methods for forming same | — | 2009-02-17 |
| 7491994 | Ferromagnetic memory cell and methods of making and using the same | Herbert L. Ho, Louis L. Hsu, Jack A. Mandelman | 2009-02-17 |
| 7488642 | Process for forming a buried plate | Ramachandra Divakaruni | 2009-02-10 |
| 7485525 | Method of manufacturing a multiple port memory having a plurality of parallel connected trench capacitors in a cell | Ramachandra Divakaruni, Jack A. Mandelman, Carl Radens, Geng Wang | 2009-02-03 |
| 7482672 | Semiconductor device structures for bipolar junction transistors | Louis L. Hsu, Jack A. Mandelman | 2009-01-27 |
| 7476578 | Process for finFET spacer formation | Xi Li, Richard S. Wise | 2009-01-13 |
| 7468538 | Strained silicon on a SiGe on SOI substrate | Dureseti Chidambarrao | 2008-12-23 |
| 7465642 | Methods for forming semiconductor structures with buried isolation collars | Jack A. Mandelman | 2008-12-16 |
| 7459743 | Dual port gain cell with side and top gated read transistor | Jack A. Mandelman, Ramachandra Divakaruni, Carl Radens, Geng Wang | 2008-12-02 |
| 7445988 | Trench memory | Geng Wang | 2008-11-04 |
| 7445987 | Offset vertical device | Ramachandra Divakaruni, Geng Wang | 2008-11-04 |