JI

Joseph A. Iadanza

IBM: 87 patents #736 of 70,183Top 2%
NT Nanya Technology: 3 patents #232 of 775Top 30%
📍 South Burlington, VT: #16 of 1,136 inventorsTop 2%
🗺 Vermont: #61 of 4,968 inventorsTop 2%
Overall (All Time): #17,987 of 4,157,543Top 1%
90
Patents All Time

Issued Patents All Time

Showing 51–75 of 90 patents

Patent #TitleCo-InventorsDate
7313178 Transceiver for receiving and transmitting data over a network and method for testing the same 2007-12-25
7307467 Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices Kenneth J. Goodnow, Edward J. Nowak, Douglas W. Stout 2007-12-11
7268632 Structure and method for providing gate leakage isolation locally within analog circuits Anthony R. Bonaccio, Hayden C. Cranford, Jr., Stephen D. Wyatt 2007-09-11
7257788 Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits Allen Haar, Sebastian T. Ventrone, Ivan L. Wemple 2007-08-14
7218135 Method and apparatus for reducing noise in a dynamic manner Igor Arsovski, Hayden C. Cranford, Jr., Sebastian T. Ventrone 2007-05-15
7089512 Method for optimal use of direct fit and interpolated models in schematic custom design of electrical circuits Raminderpal Singh 2006-08-08
7000214 Method for designing an integrated circuit having multiple voltage domains Raminderpal Singh, Sebastian T. Ventrone, Ivan L. Wemple 2006-02-14
6960837 Method of connecting core I/O pins to backside chip I/O pads 2005-11-01
6927590 Method and circuit for testing a regulated power supply in an integrated circuit 2005-08-09
6882230 System and method for control parameter re-centering in a controlled phase lock loop system Ram Kelkar, Stephen D. Wyatt 2005-04-19
6717997 Apparatus and method for current demand distribution in electronic systems Hayden C. Cranford, Jr. 2004-04-06
6683345 Semiconductor device and method for making the device having an electrically modulated conduction channel Eric Adler, James S. Dunn, Jenifer E. Lary, Kent E. Morrett, Josef S. Watts 2004-01-27
6636995 Method of automatic latch insertion for testing application specific integrated circuits Alvar A. Dean, David E. Lackey, Sebastian T. Ventrone 2003-10-21
6545521 Low skew, power sequence independent CMOS receiver device Bret Roberts Dale, Douglas W. Stout, Sebastian T. Ventrone, Hongfei Wu 2003-04-08
6487701 System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technology Alvar A. Dean, Jerry D. Hayes, Emory D. Keller, Sebastian T. Ventrone 2002-11-26
6334169 System and method for improved bitwrite capability in a field programmable memory array Ralph David Kilmoyer 2001-12-25
6298458 System and method for manufacturing test of a physical layer transceiver Hayden C. Cranford, Jr., Eirik L. Gude, Paul Owczarski, Jonathan H. Raymond 2001-10-02
6233191 Field programmable memory array Scott Whitney Gould, Frank Ray Keyser, III 2001-05-15
6130854 Programmable address decoder for field programmable memory array Scott Whitney Gould, Frank Ray Keyser, III, Terrance John Zittritsch 2000-10-10
6118707 Method of operating a field programmable memory array with a field programmable gate array Scott Whitney Gould, Frank Ray Keyser, III, Terrance John Zittritsch 2000-09-12
6091645 Programmable read ports and write ports for I/O buses in a field programmable memory array 2000-07-18
6075745 Field programmable memory array Scott Whitney Gould, Frank Ray Keyser, III, Victor Paul Seidel, Terrance John Zittritsch 2000-06-13
6044031 Programmable bit line drive modes for memory arrays Frank Ray Keyser, III 2000-03-28
6038192 Memory cells for field programmable memory array Kim P. N. Clinton, Frank Ray Keyser, III, Victor Paul Seidel, Terrance John Zittritsch 2000-03-14
6023421 Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array Kim P. N. Clinton, Scott Whitney Gould, Frank Ray Keyser, III, Ralph David Kilmoyer, Michael Joseph Laramie +2 more 2000-02-08