Issued Patents All Time
Showing 176–200 of 259 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9898331 | Dynamic releasing of cache lines | Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel | 2018-02-20 |
| 9898290 | Efficiency for coordinated start interpretive execution exit for a multithreaded processor | Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +4 more | 2018-02-20 |
| 9898289 | Coordinated start interpretive execution exit for a multithreaded processor | Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +4 more | 2018-02-20 |
| 9880811 | Reproducible stochastic rounding for out of order processors | Steven R. Carlough, Brian R. Prasky, Eric M. Schwarz | 2018-01-30 |
| 9858074 | Non-default instruction handling within transaction | Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz, Valentina Salapura, Chung-Lung K. Shum | 2018-01-02 |
| 9846593 | Predicting the length of a transaction | Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum +1 more | 2017-12-19 |
| 9836405 | Dynamic management of virtual memory blocks exempted from cache memory access | Dan F. Greiner, Michael K. Gschwind, Christian Jacobi, Younes Manton, Anthony Saporito +1 more | 2017-12-05 |
| 9830185 | Indicating nearing the completion of a transaction | Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Chung-Lung K. Shum | 2017-11-28 |
| 9823926 | Vector element rotate and insert under mask instruction | Robert F. Enenkel, Eric M. Schwarz, Timothy J. Slegel | 2017-11-21 |
| 9823924 | Vector element rotate and insert under mask instruction | Robert F. Enenkel, Eric M. Schwarz, Timothy J. Slegel | 2017-11-21 |
| 9804847 | Thread context preservation in a multithreading computer system | Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +4 more | 2017-10-31 |
| 9804840 | Vector Galois Field Multiply Sum and Accumulate instruction | — | 2017-10-31 |
| 9804846 | Thread context preservation in a multithreading computer system | Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +4 more | 2017-10-31 |
| 9785435 | Floating point instruction with selectable comparison attributes | Michael K. Gschwind, Silvia M. Mueller, Brett Olsson, Eric M. Schwarz | 2017-10-10 |
| 9778932 | Vector generate mask instruction | Robert F. Enenkel, Eric M. Schwarz, Timothy J. Slegel | 2017-10-03 |
| 9772843 | Vector find element equal instruction | Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2017-09-26 |
| 9772867 | Control area for managing multiple threads in a computer | Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +4 more | 2017-09-26 |
| 9760302 | Servicing multiple counters based on a single access check | Jane H. Bartik, Daniel V. Rosa, Donald W. Schmidt | 2017-09-12 |
| 9760511 | Efficient interruption routing for a multithreaded processor | Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +7 more | 2017-09-12 |
| 9740482 | Vector generate mask instruction | Robert F. Enenkel, Eric M. Schwarz, Timothy J. Slegel | 2017-08-22 |
| 9740483 | Vector checksum instruction | Eric M. Schwarz | 2017-08-22 |
| 9740614 | Processor directly storing address range of co-processor memory accesses in a transactional memory where co-processor supplements functions of the processor | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2017-08-22 |
| 9740615 | Processor directly storing address range of co-processor memory accesses in a transactional memory where co-processor supplements functions of the processor | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2017-08-22 |
| 9731208 | Methods of playing video games | Daniel Stelung | 2017-08-15 |
| 9733938 | Vector checksum instruction | Eric M. Schwarz | 2017-08-15 |