Issued Patents All Time
Showing 151–175 of 259 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10169243 | Reducing over-purging of structures associated with address translation | Christian Jacobi, Anthony Saporito | 2019-01-01 |
| 10168902 | Reducing purging of structures associated with address translation | Lisa C. Heller, Christian Jacobi, Anthony Saporito | 2019-01-01 |
| 10168961 | Hardware transaction transient conflict resolution | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum +1 more | 2019-01-01 |
| 10169267 | Transactional execution enabled supervisor call interruption while in TX mode | Dan F. Greiner, Michael K. Gschwind, Chung-Lung K. Shum | 2019-01-01 |
| 10162764 | Marking page table/page status table entries to indicate memory used to back address translation structures | Michael K. Gschwind | 2018-12-25 |
| 10146534 | Vector Galois field multiply sum and accumulate instruction | — | 2018-12-04 |
| 10127015 | Decimal multiply and shift instruction | Steven R. Carlough, Reid T. Copeland, Silvia M. Mueller | 2018-11-13 |
| 10102004 | Hardware counters to track utilization in a multithreading computer system | Jane H. Bartik, Gary M. King, Daniel V. Rosa, Donald W. Schmidt | 2018-10-16 |
| 10101998 | Vector checksum instruction | Eric M. Schwarz | 2018-10-16 |
| 10095523 | Hardware counters to track utilization in a multithreading computer system | Jane H. Bartik, Gary M. King, Daniel V. Rosa, Donald W. Schmidt | 2018-10-09 |
| 10083008 | Reproducible stochastic rounding for out of order processors | Steven R. Carlough, Brian R. Prasky, Eric M. Schwarz | 2018-09-25 |
| 9971629 | Dynamic releasing of cache lines | Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel | 2018-05-15 |
| 9959117 | Instruction to load data up to a specified memory boundary indicated by the instruction | Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel | 2018-05-01 |
| 9959118 | Instruction to load data up to a dynamically determined memory boundary | Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel | 2018-05-01 |
| 9952804 | Hardware transaction transient conflict resolution | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum +1 more | 2018-04-24 |
| 9952862 | Instruction to load data up to a dynamically determined memory boundary | Michael K. Gschwind, Christian Jacobi, Eric M. Schwartz, Timothy J. Slegel | 2018-04-24 |
| 9952976 | Allowing non-cacheable loads within a transaction | Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2018-04-24 |
| 9946494 | Hardware transaction transient conflict resolution | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum +1 more | 2018-04-17 |
| 9946542 | Instruction to load data up to a specified memory boundary indicated by the instruction | Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel | 2018-04-17 |
| 9940102 | Partial stochastic rounding that includes sticky and guard bits | Steven R. Carlough, Brian R. Prasky, Eric M. Schwarz | 2018-04-10 |
| 9921848 | Address expansion and contraction in a multithreading computer system | Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +4 more | 2018-03-20 |
| 9921849 | Address expansion and contraction in a multithreading computer system | Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +4 more | 2018-03-20 |
| 9916159 | Programmable linear feedback shift register | Steven R. Carlough, Brian R. Prasky, Eric M. Schwarz | 2018-03-13 |
| 9910769 | Alignment based block concurrency for accessing memory | Michael K. Gschwind, Christian Jacobi, Timothy J. Slegel | 2018-03-06 |
| 9904618 | Alignment based block concurrency for accessing memory | Michael K. Gschwind, Christian Jacobi, Timothy J. Slegel | 2018-02-27 |