Issued Patents All Time
Showing 51–75 of 133 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10546971 | Photodetector having a tunable junction region doping profile configured to improve contact resistance performance | Ning Li, Devendra K. Sadana, Yao Yao | 2020-01-28 |
| 10546745 | Semiconductor processing method | Yun Seog Lee, Devendra K. Sadana, Marinus Hopstaken | 2020-01-28 |
| 10541130 | Indium gallium arsenide surface passivation by sulfur vapor treatment | Yun Seog Lee, Talia S. Gershon, Devendra K. Sadana | 2020-01-21 |
| 10541135 | Source and drain formation using self-aligned processes | Seyoung Kim, Yun Seog Lee, Devendra K. Sadana | 2020-01-21 |
| 10541131 | Indium gallium arsenide surface passivation by sulfur vapor treatment | Yun Seog Lee, Talia S. Gershon, Devendra K. Sadana | 2020-01-21 |
| 10541129 | Indium gallium arsenide surface passivation by sulfur vapor treatment | Yun Seog Lee, Talia S. Gershon, Devendra K. Sadana | 2020-01-21 |
| 10438858 | Low-cost SOI FinFET technology | Stephen W. Bedell, Alexander Reznicek, Devendra K. Sadana, Dominic J. Schepis | 2019-10-08 |
| 10431672 | Method of forming a III-V and Zn based finFET structure using low temperature deposition techniques | Yun Seog Lee, Devendra K. Sadana, Brent A. Wacaser | 2019-10-01 |
| 10396182 | Silicon germanium-on-insulator formation by thermal mixing | Stephen W. Bedell, Jeehwan Kim, Devendra K. Sadana | 2019-08-27 |
| 10396229 | Solar cell with interdigitated back contacts formed from high and low work-function-tuned silicides of the same metal | Harold J. Hovel, Daniel A. Inns, Jeehwan Kim, Christian Lavoie, Devendra K. Sadana +3 more | 2019-08-27 |
| 10381479 | Interface charge reduction for SiGe surface | Devendra K. Sadana, Dechao Guo, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki +3 more | 2019-08-13 |
| 10354880 | Sidewall spacer with controlled geometry | Yun Seog Lee, Devendra K. Sadana | 2019-07-16 |
| 10290719 | Indium gallium arsenide metal oxide semiconductor field effect transistor having a low contact resistance to metal electrode | Ning Li, Yun Seog Lee, Devendra K. Sadana | 2019-05-14 |
| 10276816 | Illumination sensitive current control device | Bahman Hekmatshoartabari, Daniel M. Kuchta, Devendra K. Sadana | 2019-04-30 |
| 10249737 | Silicon germanium-on-insulator formation by thermal mixing | Stephen W. Bedell, Jeehwan Kim, Devendra K. Sadana | 2019-04-02 |
| 10204823 | Enhancing robustness of SOI substrate containing a buried N+ silicon layer for CMOS processing | Stephen W. Bedell, Stephan A. Cohen, Karen A. Nummy, Daniel J. Poindexter, Devendra K. Sadana | 2019-02-12 |
| 10192161 | Lithium-drift based resistive processing unit for accelerating machine learning training | Babar A. Khan, Arvind Kumar, Yun Seog Lee, Ning Li, Devendra K. Sadana | 2019-01-29 |
| 10177062 | Surface passivation having reduced interface defect density | Yun Seog Lee, Kunal Mukherjee, Devendra K. Sadana | 2019-01-08 |
| 10170388 | Surface passivation having reduced interface defect density | Yun Seog Lee, Kunal Mukherjee, Devendra K. Sadana | 2019-01-01 |
| 10164014 | MOSFET with ultra low drain leakage | Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana | 2018-12-25 |
| 10158039 | Heterojunction diode having a narrow bandgap semiconductor | Yun Seog Lee, Ning Li, Devendra K. Sadana, Yao Yao | 2018-12-18 |
| 10157993 | Low resistance contact for semiconductor devices | Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser | 2018-12-18 |
| 10153159 | Source and drain formation using self-aligned processes | Seyoung Kim, Yun Seog Lee, Devendra K. Sadana | 2018-12-11 |
| 10134601 | Zinc oxide-based mask for selective reactive ion etching | Yun Seog Lee, Devendra K. Sadana | 2018-11-20 |
| 10103111 | Semiconductor chip having tampering feature | Ali Afzali-Ardakani, Bahman Hekmatshoartabari, Daniel M. Kuchta, Devendra K. Sadana | 2018-10-16 |