Issued Patents All Time
Showing 76–100 of 133 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10096737 | Semiconductor chip having tampering feature | Ali Afzali-Ardakani, Bahman Hekmatshoartabari, Daniel M. Kuchta, Devendra K. Sadana | 2018-10-09 |
| 10079341 | Three-terminal non-volatile multi-state memory for cognitive computing applications | Stephen W. Bedell, Kevin W. Brew, Seyoung Kim, Ning Li, Yun Seog Lee +1 more | 2018-09-18 |
| 10038057 | Junction interlayer dielectric for reducing leakage current in semiconductor devices | Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser | 2018-07-31 |
| 10032870 | Low defect III-V semiconductor template on porous silicon | Keith E. Fogel, Alexander Reznicek, Dominic J. Schepis | 2018-07-24 |
| 10032730 | Semiconductor chip having tampering feature | Ali Afzali-Ardakani, Bahman Hekmatshoartabari, Daniel M. Kuchta, Devendra K. Sadana | 2018-07-24 |
| 10014322 | Local SOI fins with multiple heights | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis | 2018-07-03 |
| 10002929 | Reduction of defect induced leakage in III-V semiconductor devices | Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser | 2018-06-19 |
| 9984949 | Surface passivation having reduced interface defect density | Yun Seog Lee, Kunal Mukherjee, Devendra K. Sadana | 2018-05-29 |
| 9922866 | Enhancing robustness of SOI substrate containing a buried N+ silicon layer for CMOS processing | Stephen W. Bedell, Stephan A. Cohen, Karen A. Nummy, Daniel J. Poindexter, Devendra K. Sadana | 2018-03-20 |
| 9916984 | Self-aligned source and drain regions for semiconductor devices | Bahman Hekmatshoartabari, Jeehwan Kim, Siegfried Maurer, Devendra K. Sadana | 2018-03-13 |
| 9905637 | Reduction of defect induced leakage in III-V semiconductor devices | Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser | 2018-02-27 |
| 9899274 | Low-cost SOI FinFET technology | Stephen W. Bedell, Alexander Reznicek, Devendra K. Sadana, Dominic J. Schepis | 2018-02-20 |
| 9887265 | MOSFET with ultra low drain leakage | Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana | 2018-02-06 |
| 9799747 | Low resistance contact for semiconductor devices | Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser | 2017-10-24 |
| 9786756 | Self-aligned source and drain regions for semiconductor devices | Bahman Hekmatshoartabari, Jeehwan Kim, Siegfried Maurer, Devendra K. Sadana | 2017-10-10 |
| 9768254 | Leakage-free implantation-free ETSOI transistors | Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana | 2017-09-19 |
| 9673290 | Self-aligned source and drain regions for semiconductor devices | Bahman Hekmatshoartabari, Jeehwan Kim, Siegfried Maurer, Devendra K. Sadana | 2017-06-06 |
| 9653570 | Junction interlayer dielectric for reducing leakage current in semiconductor devices | Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser | 2017-05-16 |
| 9620592 | Doped zinc oxide and n-doping to reduce junction leakage | Keith E. Fogel, Jeehwan Kim, Siegfried Maurer, Devendra K. Sadana | 2017-04-11 |
| 9601624 | SOI based FINFET with strained source-drain regions | Stephen W. Bedell, Keith E. Fogel, Alexander Reznicek, Devendra K. Sadana, Dominic J. Schepis | 2017-03-21 |
| 9590077 | Local SOI fins with multiple heights | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis | 2017-03-07 |
| 9583562 | Reduction of defect induced leakage in III-V semiconductor devices | Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser | 2017-02-28 |
| 9553056 | Semiconductor chip having tampering feature | Ali Afzali-Ardakani, Bahman Hekmatshoartabari, Daniel M. Kuchta, Devendra K. Sadana | 2017-01-24 |
| 9536945 | MOSFET with ultra low drain leakage | Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana | 2017-01-03 |
| 9453190 | Surface treatment of textured silicon | Whitney T. Byron, Ning Li, Devendra K. Sadana | 2016-09-27 |