Issued Patents All Time
Showing 51–62 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5134616 | Dynamic RAM with on-chip ECC and optimized bit and word redundancy | John E. Barth, Jr., Charles E. Drake, John A. Fifield, William Paul Hovis, Scott C. Lewis +3 more | 1992-07-28 |
| 5058115 | Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature | Robert M. Blake, Douglas Craig Bossen, Chin-Long Chen, John A. Fifield, Tin-Chee Lo | 1991-10-15 |
| 5031151 | Wordline drive inhibit circuit implementing worldline redundancy without an access time penalty | John A. Fifield, Christopher P. Miller, Steven W. Thomashot | 1991-07-09 |
| 5015880 | CMOS driver circuit | Charles E. Drake, Scott C. Lewis | 1991-05-14 |
| 5010524 | Crosstalk-shielded-bit-line dram | John A. Fifield | 1991-04-23 |
| 4999815 | Low power addressing systems | John E. Barth, Jr., Charles E. Drake, William Paul Hovis, Gordon A. Kelley, Jr., Scott C. Lewis +2 more | 1991-03-12 |
| 4782250 | CMOS off-chip driver circuits | Robert Dean Adams, Roy C. Flaker, Kenneth S. Gray | 1988-11-01 |
| 4603341 | Stacked double dense read only memory | Claude L. Bertin | 1986-07-29 |
| 4566022 | Flexible/compressed array macro design | Donald B. Kiley | 1986-01-21 |
| 4506341 | Interlaced programmable logic array having shared elements | Francis W. Wiedman | 1985-03-19 |
| 4375085 | Dense electrically alterable read only memory | Gary D. Grise, Ning Hsieh, Chung H. Lam | 1983-02-22 |
| 4363110 | Non-volatile dynamic RAM cell | Harish N. Kotecha, Parsotam T. Patel | 1982-12-07 |