Issued Patents All Time
Showing 26–50 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9230637 | SRAM circuit with increased write margin | Shahid Butt, Pamela Castalino | 2016-01-05 |
| 9183906 | Fine granularity power gating | Chad A. Adams | 2015-11-10 |
| 9123439 | SRAM write-assisted operation with VDD-to-VCS level shifting | — | 2015-09-01 |
| 9058046 | Leakage-aware voltage regulation circuit and method | Richard Wu | 2015-06-16 |
| 8654594 | Vdiff max limiter in SRAMs for improved yield and power | Igor Arsovski, George M. Braceras | 2014-02-18 |
| 8630139 | Dual power supply memory array having a control circuit that dynamically selects a lower of two supply voltages for bitline pre-charge operations and an associated method | George M. Braceras, Kirk D. Peterson | 2014-01-14 |
| 8611164 | Device and method for detecting resistive defect | George M. Braceras, George E. Rudgers | 2013-12-17 |
| 8611169 | Fine granularity power gating | Robert M. Houle, Steven H. Lamphier | 2013-12-17 |
| 8582351 | Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability | Igor Arsovski, George M. Braceras, Kevin W. Gorman, Robert M. Houle | 2013-11-12 |
| 8437201 | Word-line level shift circuit | Igor Arsovski, Matthew W. Deming, Darryl R. Hill, Reid A. Wistort | 2013-05-07 |
| 8363453 | Static random access memory (SRAM) write assist circuit with leakage suppression and level control | Igor Arsovski, Vinod Ramadurai | 2013-01-29 |
| 8279687 | Single supply sub VDD bit-line precharge SRAM and method for level shifting | Chad A. Adams, George M. Braceras, Daniel Mark Nelson, Vinod Ramadurai | 2012-10-02 |
| 8233337 | SRAM delay circuit that tracks bitcell characteristics | Igor Arsovski, George M. Braceras, Robert M. Houle | 2012-07-31 |
| 8233342 | Apparatus and method for implementing write assist for static random access memory arrays | Chad A. Adams, George M. Braceras, Fred J. Towler | 2012-07-31 |
| 8228713 | SRAM having wordline up-level voltage adjustable to assist bitcell stability and design structure for same | Igor Arsovski, John A. Fifield, Robert M. Houle | 2012-07-24 |
| 8218378 | Word-line level shift circuit | Igor Arsovski, Matthew W. Deming, Darryl R. Hill, Reid A. Wistort | 2012-07-10 |
| 8027207 | Leakage compensated reference voltage generation system | John A. Fifield | 2011-09-27 |
| 7904658 | Structure for power-efficient cache memory | Wagdi W. Abadeer, George M. Braceras, John A. Fifield | 2011-03-08 |
| 7894291 | Circuit and method for controlling a standby voltage level of a memory | George M. Braceras, John A. Fifield | 2011-02-22 |
| 7826288 | Device threshold calibration through state dependent burn-in | Igor Arsovski, Michael A. Ziegerhofer | 2010-11-02 |
| 7817481 | Column selectable self-biasing virtual voltages for SRAM write assist | Chad A. Adams, George M. Braceras, Todd A. Christensen | 2010-10-19 |
| 7791977 | Design structure for low overhead switched header power savings apparatus | John E. Barth, Jr., Vinod Ramadurai | 2010-09-07 |
| 7724565 | Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices | John E. Barth, Jr., Geordie M. Braceras | 2010-05-25 |
| 7716619 | Design structure for implementing dynamic data path with interlocked keeper and restore devices | Geordie M. Braceras, John A. Fifield | 2010-05-11 |
| 7643357 | System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture | George M. Braceras, Steven H. Lamphier, Vinod Ramadurai | 2010-01-05 |