Issued Patents All Time
Showing 76–100 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6922076 | Scalable termination | George M. Braceras, Reid C. Hutchins | 2005-07-26 |
| 6915467 | System and method for testing a column redundancy of an integrated circuit memory | — | 2005-07-05 |
| 6912165 | Method for transparent updates of output driver impedance | Phillip L. Corson | 2005-06-28 |
| 6897674 | Adaptive integrated circuit based on transistor current measurements | George M. Braceras | 2005-05-24 |
| 6854041 | DRAM-based separate I/O memory solution for communication applications | James J. Covino, Kevin G. Petrunich | 2005-02-08 |
| 6754135 | Reduced latency wide-I/O burst architecture | — | 2004-06-22 |
| 6509778 | BIST circuit for variable impedance system | George M. Braceras, Steven Burns, Patrick R. Hansen | 2003-01-21 |
| 6510091 | Dynamic precharge decode scheme for fast DRAM | George M. Braceras | 2003-01-21 |
| 6504766 | System and method for early write to memory by injecting small voltage signal | John E. Barth, Jr. | 2003-01-07 |
| 6501675 | Alternating reference wordline scheme for fast DRAM | Robert E. Busch | 2002-12-31 |
| 6449200 | Duty-cycle-efficient SRAM cell test | Erik A. Nelson | 2002-09-10 |
| 6400629 | System and method for early write to memory by holding bitline at fixed potential | John E. Barth, Jr. | 2002-06-04 |
| 6392949 | High performance memory architecture | George M. Braceras | 2002-05-21 |
| 6327224 | On-chip method for measuring access time and data-pin spread | Geordie M. Braceras, Dale E. Pontius | 2001-12-04 |
| 6219288 | Memory having user programmable AC timings | Geordie M. Braceras, Steven H. Lamphier | 2001-04-17 |
| 6208572 | Semiconductor memory device having resistive bitline contact testing | R. Dean Adams, Robert E. Busch, George E. Rudgers | 2001-03-27 |
| 6198666 | Control input timing-independent dynamic multiplexer circuit | — | 2001-03-06 |
| 6133749 | Variable impedance output driver circuit using analog biases to match driver output impedance to load input impedance | Patrick R. Hansen | 2000-10-17 |
| 6134182 | Cycle independent data to echo clock tracking circuit | James J. Covino | 2000-10-17 |
| 6038181 | Efficient semiconductor burn-in circuit and method of operation | George M. Braceras, James J. Covino, Richard E. Hee | 2000-03-14 |
| 5978929 | Computer unit responsive to difference between external clock period and circuit characteristic period | Jim Covino | 1999-11-02 |
| 5666078 | Programmable impedance output driver | Steven H. Lamphier, Michael J. Schneiderwind, Fred J. Towler | 1997-09-09 |
| 5659508 | Special mode enable transparent to normal mode operation | Steven H. Lamphier, Kevin G. Petrunich, Ronald DeSales Rossi, Roger Andrew Verhelst, Paul Stafford Zerr | 1997-08-19 |
| 5606526 | Glitch-free dual clok read circuit | — | 1997-02-25 |
| 5343428 | Memory having a latching BICMOS sense amplifier | John D. Porter | 1994-08-30 |