Issued Patents All Time
Showing 51–75 of 124 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9495138 | Scheme for verifying the effects of program optimizations | Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum | 2016-11-15 |
| 9495157 | Fingerprint-based branch prediction | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum | 2016-11-15 |
| 9424012 | Programmable code fingerprint | Michael K. Gschwind, Christian Jacobi, Chung-Lung K. Shum | 2016-08-23 |
| 9411664 | Fingerprint-based processor parameter management | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum | 2016-08-09 |
| 9395961 | Fingerprint-based code version selection | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum | 2016-07-19 |
| 9372819 | I/O device N—port ID virtualization | Matthew J. Kalos | 2016-06-21 |
| 9342432 | Hardware performance-monitoring facility usage after context swaps | Brian R. Mestan | 2016-05-17 |
| 9342337 | Privilege level aware processor hardware resource management facility | Michael K. Gschwind, Naresh Nayar | 2016-05-17 |
| 9229716 | Time-based task priority boost management using boost register values | Christopher Francois, Bruce Mealey, Suresh E. Warrier | 2016-01-05 |
| 9189365 | Hardware-assisted program trace collection with selectable call-signature capture | David S. Levitan, Brian R. Mestan, Mauricio J. Serrano | 2015-11-17 |
| 9152426 | Initiating assist thread upon asynchronous event for processing simultaneously with controlling thread and updating its running status in status register | Venkat R. Indukuru | 2015-10-06 |
| 9069598 | Providing logical partions with hardware-thread specific information reflective of exclusive use of a processor core | Bruce Mealy, Naresh Nayar | 2015-06-30 |
| 9069629 | Bidirectional counting of dual outcome events | Venkat R. Indukuru | 2015-06-30 |
| 9047079 | Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition | Becky Bruce, Bradly G. Frey, Kumar K. Gala, Cathy May, Michael D. Snyder +2 more | 2015-06-02 |
| 8990816 | Providing logical partions with hardware-thread specific information reflective of exclusive use of a processor core | Bruce Mealy, Naresh Nayar | 2015-03-24 |
| 8984538 | Bidirectional counting of dual outcome events | Venkat R. Indukuru | 2015-03-17 |
| 8924499 | Operating system migration with minimal storage area network reconfiguration | James P. Allen, Daniel G. Eisenhauer, Robert G. Kovacs, Satya Prakesh Sharma | 2014-12-30 |
| 8898441 | Obtaining and releasing hardware threads without hypervisor involvement | Ronald P. Hall | 2014-11-25 |
| 8868886 | Task switch immunized performance monitoring | David S. Levitan, Brian R. Mestan | 2014-10-21 |
| 8793474 | Obtaining and releasing hardware threads without hypervisor involvement | Ronald P. Hall | 2014-07-29 |
| 8719554 | Scaleable status tracking of multiple assist hardware threads | Richard Louis Arndt, Ronald P. Hall | 2014-05-06 |
| 8719638 | Assist thread analysis and debug mechanism | Richard Louis Arndt | 2014-05-06 |
| 8713290 | Scaleable status tracking of multiple assist hardware threads | Richard Louis Arndt, Ronald P. Hall | 2014-04-29 |
| 8695010 | Privilege level aware processor hardware resource management facility | Michael K. Gschwind, Naresh Nayar | 2014-04-08 |
| 8694832 | Assist thread analysis and debug mechanism | Richard Louis Arndt | 2014-04-08 |