Issued Patents All Time
Showing 51–75 of 181 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9625939 | Clock forwarding over optics | Joseph J. Cahill, Kaveh Naderi, James E. Smith | 2017-04-18 |
| 9558139 | System interconnect dynamic scaling handshake using spare bit-lane | Frank D. Ferraiolo, Anand Haridass, Prasanna Jayaraman | 2017-01-31 |
| 9552319 | System interconnect dynamic scaling handshake using spare bit-lane | Frank D. Ferraiolo, Anand Haridass, Prasanna Jayaraman | 2017-01-24 |
| 9548808 | Dynamic optical channel sparing in an industry standard input/output subsystem | Patrick Allen Buckland, Nanju Na, Suzanne M. Nolen | 2017-01-17 |
| 9536604 | Impedance matching system for DDR memory | Keenan W. Franz, Nam H. Pham, Lloyd A. Walls | 2017-01-03 |
| 9529406 | System interconnect dynamic scaling by lane width and operating frequency balancing | Frank D. Ferraiolo, Anand Haridass, Prasanna Jayaraman | 2016-12-27 |
| 9524013 | System interconnect dynamic scaling by lane width and operating frequency balancing | Frank D. Ferraiolo, Anand Haridass, Prasanna Jayaraman | 2016-12-20 |
| 9474034 | Power reduction in a parallel data communications interface using clock resynchronization | Steven J. Baumgartner, Michael B. Spear | 2016-10-18 |
| 9473333 | Communications system via data scrambling and associated methods | Frank D. Ferralolo, Robert J. Reese, Martin Schmatz | 2016-10-18 |
| 9467092 | Phased locked loop with multiple voltage controlled oscillators | David M. Friend, Grant P. Kesselring, James D. Strom | 2016-10-11 |
| 9459982 | Bus interface optimization by selecting bit-lanes having best performance margins | Frank D. Ferraiolo, Anand Haridass, Prasanna Jayaraman | 2016-10-04 |
| 9456506 | Packaging for eight-socket one-hop SMP topology | John L. Colbert, Paul M. Harvey, Rohan U. Mandrekar | 2016-09-27 |
| 9445507 | Packaging for eight-socket one-hop SMP topology | John L. Colbert, Paul M. Harvey, Rohan U. Mandrekar | 2016-09-13 |
| 9442512 | Interface clock frequency switching using a computed insertion delay | Paul W. Coteus, Hillery C. Hunter, Kyu-hyoun Kim, Glen A. Wiedemeier | 2016-09-13 |
| 9411750 | Efficient calibration of a low power parallel data communications channel | Timothy O. Dickson, Frank D. Ferraiolo, Douglas J. Joseph | 2016-08-09 |
| 9368852 | Method for performing frequency band splitting | Jose A. Hejase, Rubina F. Ahmed, James D. Jordan, Nam H. Pham, Lloyd A. Walls | 2016-06-14 |
| 9324031 | System interconnect dynamic scaling by predicting I/O requirements | Frank D. Ferraiolo, Anand Haridass, Prasanna Jayaraman, David J. Krolak | 2016-04-26 |
| 9324030 | System interconnect dynamic scaling by predicting I/O requirements | Frank D. Ferraiolo, Anand Haridass, Prasanna Jayaraman, David J. Krolak | 2016-04-26 |
| 9244799 | Bus interface optimization by selecting bit-lanes having best performance margins | Frank D. Ferraiolo, Anand Haridass, Prasanna Jayaraman | 2016-01-26 |
| 9235543 | Systems for signal detection | Hayden C. Cranford, Jr., William R. Kelly | 2016-01-12 |
| 9232646 | High speed differential wiring in glass ceramic MCMS | Jinwoo Choi, Rohan U. Mandrekar | 2016-01-05 |
| 9232645 | High speed differential wiring in glass ceramic MCMS | Jinwoo Choi, Rohan U. Mandrekar | 2016-01-05 |
| 9231796 | Power aware equalization in a serial communications link | John F. Bulzacchelli, Hayden C. Cranford, Jr., David W. Siljenberg | 2016-01-05 |
| 9219473 | Overvoltage protection circuit | — | 2015-12-22 |
| 9213667 | Systems and methods for signal detection | Hayden C. Cranford, Jr., William R. Kelly | 2015-12-15 |