Issued Patents All Time
Showing 76–100 of 264 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9996472 | Extract target cache attribute facility and instruction therefor | Timothy Siegel | 2018-06-12 |
| 9996360 | Transaction abort instruction specifying a reason for abort | Christian Jacobi, Marcel Mitran, Timothy J. Slegel | 2018-06-12 |
| 9996355 | Parsing-enhancement facility | John R. Ehrman | 2018-06-12 |
| 9996349 | Clearing specified blocks of main storage | Anthony F. Coneski, Beth A. Glendening, Peter G. Sutton, Scott B. Tuttle, Elpida Tzortzatos | 2018-06-12 |
| 9983883 | Transaction abort instruction specifying a reason for abort | Christian Jacobi, Marcel Mitran, Timothy J. Slegel | 2018-05-29 |
| 9983882 | Selectively controlling instruction execution in transactional processing | Christian Jacobi, Robert R. Rogers, Timothy J. Slegel | 2018-05-29 |
| 9983881 | Selectively controlling instruction execution in transactional processing | Christian Jacobi, Robert R. Rogers, Timothy J. Slegel | 2018-05-29 |
| 9934159 | Dynamic address translation with fetch protection in an emulated environment | Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel +1 more | 2018-04-03 |
| 9921872 | Interprocessor memory status communication | Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-03-20 |
| 9921849 | Address expansion and contraction in a multithreading computer system | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Lisa C. Heller +4 more | 2018-03-20 |
| 9921848 | Address expansion and contraction in a multithreading computer system | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Lisa C. Heller +4 more | 2018-03-20 |
| 9921834 | Prefetching of discontiguous storage locations in anticipation of transactional execution | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2018-03-20 |
| 9904572 | Dynamic prediction of hardware transaction resource requirements | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2018-02-27 |
| 9898289 | Coordinated start interpretive execution exit for a multithreaded processor | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Lisa C. Heller +4 more | 2018-02-20 |
| 9898290 | Efficiency for coordinated start interpretive execution exit for a multithreaded processor | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Lisa C. Heller +4 more | 2018-02-20 |
| 9886392 | Selective purging of PCI I/O address translation buffer | David F. Craddock, Thomas A. Gregg, Damian L. Osisek | 2018-02-06 |
| 9886391 | Selective purging of PCI I/O address translation buffer | David F. Craddock, Thomas A. Gregg, Damian L. Osisek | 2018-02-06 |
| 9880942 | Selective purging of PCI I/O address translation buffer | David F. Craddock, Thomas A. Gregg, Damian L. Osisek | 2018-01-30 |
| 9864692 | Managing read tags in a transactional memory | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-01-09 |
| 9860056 | Instruction for performing a pseudorandom number seed operation | Bernd Nerz, Tamas Visegrady | 2018-01-02 |
| 9858082 | Restricted instructions in transactional execution | Christian Jacobi, Timothy J. Slegel | 2018-01-02 |
| 9851969 | Function virtualization facility for function query of a processor | Damian L. Osisek, Timothy J. Slegel | 2017-12-26 |
| 9851978 | Restricted instructions in transactional execution | Christian Jacobi, Timothy J. Slegel | 2017-12-26 |
| 9836405 | Dynamic management of virtual memory blocks exempted from cache memory access | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Younes Manton, Anthony Saporito +1 more | 2017-12-05 |
| 9830185 | Indicating nearing the completion of a transaction | Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Chung-Lung K. Shum | 2017-11-28 |