Issued Patents All Time
Showing 51–75 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7330925 | Transaction flow control mechanism for a bus bridge | Charles S. Woodruff | 2008-02-12 |
| 7319729 | Asynchronous interface methods and apparatus | Seetharam Gundurao, Kenneth A. Lauricella, Nishant Sharma, Richard N. Wilson | 2008-01-15 |
| 7304493 | FPGA powerup to known functional state | Kenneth J. Goodnow, Christopher B. Reynolds, Jack R. Smith, Sebastian T. Ventrone, Keith R. Williams | 2007-12-04 |
| 7289444 | Method for providing bounded latency in a real-time data processing system | — | 2007-10-30 |
| 7282949 | FPGA powerup to known functional state | Kenneth J. Goodnow, Christopher B. Reynolds, Jack R. Smith, Sebastian T. Ventrone, Keith R. Williams | 2007-10-16 |
| 7275124 | Method and system for controlling forwarding or terminating of a request at a bus interface based on buffer availability | Charles S. Woodruff | 2007-09-25 |
| 7275125 | Pipeline bit handling circuit and method for a bus bridge | Robert Allen Drehmel, Charles S. Woodruff | 2007-09-25 |
| 7234017 | Computer system architecture for a processor connected to a high speed bus transceiver | Giora Biran, Matthew Adam Cushing, Robert Allen Drehmel, Allen James Gavin, Mark E. Kautzman +8 more | 2007-06-19 |
| 7213084 | System and method for allocating memory allocation bandwidth by assigning fixed priority of access to DMA machines and programmable priority to processing unit | Randall R. Pratt, Sebastian T. Ventrone | 2007-05-01 |
| 7206886 | Data ordering translation between linear and interleaved domains at a bus interface | Robert S. Horton, Charles S. Woodruff | 2007-04-17 |
| 7194567 | Method and system for ordering requests at a bus interface | Charles S. Woodruff | 2007-03-20 |
| 7134104 | Method of selectively building redundant logic structures to improve fault tolerance | Kenneth J. Goodnow, Jack R. Smith, Sebastian T. Ventrone | 2006-11-07 |
| 7065733 | Method for modifying the behavior of a state machine | Kenneth J. Goodnow, Christ pher B. Reynolds, Jack R. Smith, Sebastian T. Ventrone | 2006-06-20 |
| 7065602 | Circuit and method for pipelined insertion | Robert S. Horton, David W. Milton, Paul M. Schanely, Sebastian T. Ventrone | 2006-06-20 |
| 6996795 | Data processing in digital systems | Kenneth J. Goodnow, Sebastian T. Ventrone | 2006-02-07 |
| 6954085 | System and method for dynamically executing a function in a programmable logic array | Kenneth J. Goodnow, Christopher B. Reynolds, Jack R. Smith, Sebastian T. Ventrone | 2005-10-11 |
| 6658634 | Logic power optimization algorithm | Kenneth J. Goodnow, Michel S. Michail, Wilbur D. Pricer, Sebastian T. Ventrone | 2003-12-02 |
| 6487699 | Method of controlling external models in system-on-chip verification | Robert J. Devins, Robert D. Herzl, David W. Milton | 2002-11-26 |
| 6446163 | Memory card with signal processing element | Bruce G. Hazelzet, Christopher P. Miller, Paul C. Stabler | 2002-09-03 |
| 6385685 | Memory card utilizing two wire bus | Timothy J. Dell, Bruce G. Hazelzet, Mark W. Kellogg, Paul C. Stabler | 2002-05-07 |
| 6321312 | System and method for controlling peripheral device memory access in a data processing system | Gordon Taylor Davis, Llewellyn Bradley Marshall, IV, Paul C. Stabler | 2001-11-20 |
| 6260116 | System and method for prefetching data | Gordon Taylor Davis, Llewellyn Bradley Marshall, IV, Paul C. Stabler | 2001-07-10 |
| 6233639 | Memory card utilizing two wire bus | Timothy J. Dell, Bruce G. Hazelzet, Mark W. Kellogg, Paul C. Stabler | 2001-05-15 |
| 6157981 | Real time invariant behavior cache | Bartholomew Blaner, Henry Harvey Burkhart, Robert D. Herzl, Kenneth A. Lauricella, Arnold S. Tran | 2000-12-05 |
| 6138200 | System for allocating bus bandwidth by assigning priority for each bus duration time slot to application using bus frame and bus duration | — | 2000-10-24 |