Issued Patents All Time
Showing 51–75 of 130 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9773812 | Integrated circuit with heterogeneous CMOS integration of strained silicon germanium and group III-V semiconductor materials and method to fabricate same | Pouya Hashemi, Effendi Leobandung, Alexander Reznicek | 2017-09-26 |
| 9773903 | Asymmetric III-V MOSFET on silicon substrate | Pranita Kerber, Effendi Leobandung, Amlan Majumdar, Renee T. Mo, Yanning Sun | 2017-09-26 |
| 9735175 | Integrated circuit with heterogeneous CMOS integration of strained silicon germanium and group III-V semiconductor materials and method to fabricate same | Pouya Hashemi, Effendi Leobandung, Alexander Reznicek | 2017-08-15 |
| 9726819 | Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth | Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2017-08-08 |
| 9722031 | Reduced current leakage semiconductor device | Pranita Kerber, Young-Hee Kim, Effendi Leobandung, Yanning Sun | 2017-08-01 |
| 9711617 | Dual isolation fin and method of making | Sanghoon Lee, Effendi Leobandung | 2017-07-18 |
| 9704958 | III-V field effect transistor on a dielectric layer | Edward W. Kiewra, Amlan Majumdar, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun | 2017-07-11 |
| 9653308 | Epitaxial lift-off process with guided etching | Ning Li, Devendra K. Sadana, Leathen Shi, Kuen-Ting Shiu | 2017-05-16 |
| 9627482 | Reduced current leakage semiconductor device | Pranita Kerber, Young-Hee Kim, Effendi Leobandung, Yanning Sun | 2017-04-18 |
| 9608160 | Polarization free gallium nitride-based photonic devices on nanopatterned silicon | Can Bayram, Tayfun Gokmen, Ning Li, John A. Ott, Devendra K. Sadana +1 more | 2017-03-28 |
| 9595805 | III-V photonic integrated circuits on silicon substrate | Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2017-03-14 |
| 9590393 | Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth | Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2017-03-07 |
| 9570296 | Preparation of low defect density of III-V on Si for device fabrication | Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun | 2017-02-14 |
| 9564494 | Enhanced defect reduction for heteroepitaxy by seed shape engineering | David L. Rath, Devendra K. Sadana, Kuen-Ting Shiu, Brent A. Wacaser | 2017-02-07 |
| 9553166 | Asymmetric III-V MOSFET on silicon substrate | Pranita Kerber, Effendi Leobandung, Amlan Majumdar, Renee T. Mo, Yanning Sun | 2017-01-24 |
| 9529956 | Active region design layout | Chen-Liang Liao, Ming-Ta Lei, Yi-Lii Huang | 2016-12-27 |
| 9530643 | Selective epitaxy using epitaxy-prevention layers | Jeehwan Kim, John A. Ott, Devendra K. Sadana | 2016-12-27 |
| 9515165 | III-V field effect transistor (FET) with reduced short channel leakage, integrated circuit (IC) chip and method of manufacture | Pranita Kerber, Effendi Leobandung, Amlan Majumdar | 2016-12-06 |
| 9508640 | Multiple via structure and method | Szu-Lin Cheng, Keith E. Fogel, Edward W. Kiewra, Amlan Majumdar, Devendra K. Sadana +2 more | 2016-11-29 |
| 9508550 | Preparation of low defect density of III-V on Si for device fabrication | Devendra K. Sadana, Keun-Ting Shiu, Yanning Sun | 2016-11-29 |
| 9496347 | Graded buffer epitaxy in aspect ratio trapping | Amlan Majumdar, Kuen-Ting Shiu, Jeng-Bang Yau | 2016-11-15 |
| 9495019 | Display method of mobile device selection and terminal device | Simon Ekstrand | 2016-11-15 |
| 9472411 | Spalling using dissolvable release layer | Stephen W. Bedell, Ning Li, Devendra K. Sadana, Katherine L. Saenger | 2016-10-18 |
| 9412744 | III-V CMOS integration on silicon substrate via embedded germanium-containing layer | Devendra K. Sadana, Kuen-Ting Shiu | 2016-08-09 |
| 9406566 | Integration of III-V compound materials on silicon | Sanghoon Lee, Kuen-Ting Shiu | 2016-08-02 |