Issued Patents All Time
Showing 26–50 of 130 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10304947 | Smoothing surface roughness of III-V semiconductor fins formed from silicon mandrels by regrowth | Tze-Chiang Chen, Sanghoon Lee, Effendi Leobandung | 2019-05-28 |
| 10256608 | Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same | Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2019-04-09 |
| 10217659 | Dual isolation fin and method of making | Sanghoon Lee, Effendi Leobandung | 2019-02-26 |
| 10217632 | Integration of III-V compound materials on silicon | Sanghoon Lee, Kuen-Ting Shiu | 2019-02-26 |
| 10205003 | Surface roughness of III-V fin formed on silicon sidewall by implementing sacrificial buffers | Sanghoon Lee, Effendi Leobandung, Renee T. Mo | 2019-02-12 |
| 10141719 | Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same | Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2018-11-27 |
| 10135226 | Resonant cavity strained Group III-V photodetector and LED on silicon substrate and method to fabricate same | Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2018-11-20 |
| 10128343 | III-V MOSFET with self-aligned diffusion barrier | Kevin K. Chan, Jack O. Chu, Yanning Sun, Jeng-Bang Yau | 2018-11-13 |
| 10122153 | Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same | Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2018-11-06 |
| 10083987 | CMOS with middle of line processing of III-V material on mandrel | Sanghoon Lee, Effendi Leobandung, Renee T. Mo | 2018-09-25 |
| 10083986 | CMOS with middle of line processing of III-V material on mandrel | Sanghoon Lee, Effendi Leobandung, Renee T. Mo | 2018-09-25 |
| 10043663 | Enhanced defect reduction for heteroepitaxy by seed shape engineering | David L. Rath, Devendra K. Sadana, Kuen-Ting Shiu, Brent A. Wacaser | 2018-08-07 |
| 10037989 | III-V lateral bipolar integration with silicon | Sanghoon Lee, Effendi Leobandung, Renee T. Mo | 2018-07-31 |
| 10014377 | III-V field effect transistor on a dielectric layer | Edward W. Kiewra, Amlan Majumdar, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun | 2018-07-03 |
| 9984873 | Preparation of low defect density of III-V on Si for device fabrication | Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun | 2018-05-29 |
| 9966735 | III-V lasers with integrated silicon photonic circuits | Frank R. Libsch, Tak H. Ning, Uzma Rana, Kuen-Ting Shiu | 2018-05-08 |
| 9947755 | III-V MOSFET with self-aligned diffusion barrier | Kevin K. Chan, Jack O. Chu, Yanning Sun, Jeng-Bang Yau | 2018-04-17 |
| 9947533 | Selective epitaxy using epitaxy-prevention layers | Jeehwan Kim, John A. Ott, Devendra K. Sadana | 2018-04-17 |
| 9941363 | III-V transistor device with self-aligned doped bottom barrier | Pranita Kerber, Amlan Majumdar, Yanning Sun | 2018-04-10 |
| 9882021 | Planar III-V field effect transistor (FET) on dielectric layer | Edward W. Kiewra, Amlan Majumdar, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu +1 more | 2018-01-30 |
| 9865469 | Epitaxial lift-off process with guided etching | Ning Li, Devendra K. Sadana, Leathen Shi, Kuen-Ting Shiu | 2018-01-09 |
| 9864135 | Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxially formed material | Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2018-01-09 |
| 9853109 | III-V MOSFET with self-aligned diffusion barrier | Kevin K. Chan, Jack O. Chu, Yanning Sun, Jeng-Bang Yau | 2017-12-26 |
| 9818901 | Wafer bonded solar cells and fabrication methods | Stephen W. Bedell, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu, Norma E. Sosa Cortes | 2017-11-14 |
| 9793405 | Semiconductor lateral sidewall growth from a semiconductor pillar | Sanghoon Lee, Effendi Leobandung, Renee T. Mo, Yanning Sun | 2017-10-17 |