Issued Patents All Time
Showing 51–75 of 111 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10459031 | Electronic circuit having serial latch scan chains | Tilman Gloekler, Andreas C. Koenig, Jens Kuenzer | 2019-10-29 |
| 10437718 | Computerized methods for prefetching data based on machine learned sequences of memory addresses | Andreea Anghel, Peter Altevogt, Gero Dittmann | 2019-10-08 |
| 10379811 | Normalization of a product on a datapath | Klaus M. Kroener, Silvia M. Mueller, Andreas Wagner | 2019-08-13 |
| 10372417 | Multiply-add operations of binary numbers in an arithmetic unit | Tina Babinsky, Michael Klein, Silvia M. Mueller | 2019-08-06 |
| 10324816 | Checking a computer processor design for soft error handling | Erez Barak, Nicol Hofmann, Osher Yifrach | 2019-06-18 |
| 10318395 | Checking a computer processor design for soft error handling | Erez Barak, Nicol Hofmann, Osher Yifrach | 2019-06-11 |
| 10303481 | Performance-aware instruction scheduling | Peter Altevogt, Thomas Pflueger | 2019-05-28 |
| 10296294 | Multiply-add operations of binary numbers in an arithmetic unit | Tina Babinsky, Michael Klein, Silvia M. Mueller | 2019-05-21 |
| 10275391 | Combining of several execution units to compute a single wide scalar result | Nicol Hofmann, Michael Klein | 2019-04-30 |
| 10235135 | Normalization of a product on a datapath | Klaus M. Kroener, Silvia M. Mueller, Andreas Wagner | 2019-03-19 |
| 10228910 | Overflow detection for sign-magnitude adders | Petra Leber, Silvia M. Mueller | 2019-03-12 |
| 10169451 | Rapid character substring searching | Stefan Payer, Razvan Peter Figuli, Michael Klein | 2019-01-01 |
| 10095475 | Decimal and binary floating point rounding | Steven R. Carlough, Klaus M. Kroener, Petra Leber, Silvia M. Mueller | 2018-10-09 |
| 10088524 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Raghu G. GopalaKrishnaSetty, Mary P. Kusko | 2018-10-02 |
| 10067744 | Overflow detection for sign-magnitude adders | Petra Leber, Silvia M. Mueller | 2018-09-04 |
| 10018671 | Reducing power requirements and switching during logic built-in-self-test and scan test | Satya R. S. Bhamidipati, Mary P. Kusko | 2018-07-10 |
| 10018672 | Reducing power requirements and switching during logic built-in-self-test and scan test | Satya R. S. Bhamidipati, Mary P. Kusko | 2018-07-10 |
| 9977680 | Clock-gating for multicycle instructions | Juergen Haess, Stefan Payer, Kerstin Claudia Schelm | 2018-05-22 |
| 9959093 | Binary fused multiply-add floating-point calculations | Michael Klein, Klaus M. Kroener, Silvia M. Mueller | 2018-05-01 |
| 9952829 | Binary fused multiply-add floating-point calculations | Michael Klein, Klaus M. Kroener, Silvia M. Mueller | 2018-04-24 |
| 9940199 | Checking arithmetic computations | Steven R. Carlough, Silvia M. Mueller | 2018-04-10 |
| 9929749 | Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry | Michael Fee, Ronald J. Frishmuth, Mary P. Kusko | 2018-03-27 |
| 9923579 | Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry | Michael Fee, Ronald J. Frishmuth, Mary P. Kusko | 2018-03-20 |
| 9915701 | Bypassing an encoded latch on a chip during a test-pattern scan | Michael Fee, Ronald J. Frishmuth, Mary P. Kusko | 2018-03-13 |
| 9910090 | Bypassing an encoded latch on a chip during a test-pattern scan | Michael Fee, Ronald J. Frishmuth, Mary P. Kusko | 2018-03-06 |