Issued Patents All Time
Showing 26–50 of 111 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11042371 | Plausability-driven fault detection in result logic and condition codes for fast exact substring match | Razvan Peter Figuli, Stefan Payer, Kerstin Claudia Schelm | 2021-06-22 |
| 11023205 | Negative zero control in instruction execution | Reid T. Copeland, Petra Leber, Silvia M. Mueller, Jonathan D. Bradbury, Xin Guo | 2021-06-01 |
| 10996951 | Plausibility-driven fault detection in string termination logic for fast exact substring match | Razvan Peter Figuli, Stefan Payer, Petra Leber | 2021-05-04 |
| 10983159 | Method and apparatus for wiring multiple technology evaluation circuits | Stefan Payer, Michael Klein, Ralf Richter | 2021-04-20 |
| 10901745 | Method and apparatus for processing storage instructions | Peter Altevogt, Thomas Pflueger | 2021-01-26 |
| 10902348 | Computerized branch predictions and decisions | Peter Altevogt, Andreea Anghel, Gero Dittmann, Thomas Pflueger | 2021-01-26 |
| 10896386 | Computerized branch predictions and decisions | Peter Altevogt, Andreea Anghel, Gero Dittmann, Thomas Pflueger | 2021-01-19 |
| 10890622 | Integrated circuit control latch protection | Stefan Payer, Michael Klein, Nicol Hofmann | 2021-01-12 |
| 10782968 | Rapid substring detection within a data element string | Razvan Peter Figuli, Stefan Payer, Kerstin Claudia Schelm | 2020-09-22 |
| 10768232 | ATE compatible high-efficient functional test | Thomas Gentner, Jens Kuenzer, Martin Padeffke | 2020-09-08 |
| 10754773 | Selection of variable memory-access size | Andreea Anghel, Gero Dittmann, Peter Altevogt, Thomas Pflueger | 2020-08-25 |
| 10747819 | Rapid partial substring matching | Stefan Payer, Razvan Peter Figuli, Nicol Hofmann | 2020-08-18 |
| 10746794 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Raghu G. GopalaKrishnaSetty, Mary P. Kusko | 2020-08-18 |
| 10740098 | Aligning most significant bits of different sized elements in comparison result vectors | Silvia M. Mueller, Jens Seifert, Jörg-Stephan Vogt, Markus Lachenmayr, L'Emir Salim Chehab +2 more | 2020-08-11 |
| 10739401 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Raghu G. GopalaKrishnaSetty, Mary P. Kusko | 2020-08-11 |
| 10732972 | Non-overlapping substring detection within a data element string | Razvan Peter Figuli, Stefan Payer, Petra Leber | 2020-08-04 |
| 10684861 | Enhanced performance-aware instruction scheduling | Peter Altevogt, Thomas Pflueger | 2020-06-16 |
| 10649781 | Enhanced performance-aware instruction scheduling | Peter Altevogt, Thomas Pflueger | 2020-05-12 |
| 10649730 | Normalization of a product on a datapath | Klaus M. Kroener, Silvia M. Mueller, Andreas Wagner | 2020-05-12 |
| 10649028 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Raghu G. GopalaKrishnaSetty, Mary P. Kusko | 2020-05-12 |
| 10598727 | Identification of unknown sources for logic built-in self test in verification | Satya R. S. Bhamidipati, Mary P. Kusko, Srinivas V. N. Polisetty | 2020-03-24 |
| 10579375 | Method to build reconfigurable variable length comparators | Silvia M. Mueller, Jens Seifert, Jörg-Stephan Vogt, Markus Lachenmayr, L'Emir Salim Chehab +2 more | 2020-03-03 |
| 10558432 | Multiply-add operations of binary numbers in an arithmetic unit | Tina Babinsky, Michael Klein, Silvia M. Mueller | 2020-02-11 |
| 10552167 | Clock-gating for multicycle instructions | Juergen Haess, Stefan Payer, Kerstin Claudia Schelm | 2020-02-04 |
| 10528354 | Performance-aware instruction scheduling | Peter Altevogt, Thomas Pflueger | 2020-01-07 |