Issued Patents All Time
Showing 126–148 of 148 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9250912 | Fast index tree for accelerated branch prediction | James J. Bonanno, Brian R. Prasky | 2016-02-02 |
| 9152424 | Mitigating instruction prediction latency with independently filtered presence predictors | James J. Bonanno, Brian R. Prasky, Chung-Lung K. Shum | 2015-10-06 |
| 9152425 | Mitigating instruction prediction latency with independently filtered presence predictors | James J. Bonanno, Brian R. Prasky, Chung-Lung K. Shum | 2015-10-06 |
| 9135012 | Instruction filtering | James J. Bonanno, Adam B. Collura, Ulrich Mayer, Brian R. Prasky, Chung-Lung K. Shum | 2015-09-15 |
| 9135013 | Instruction filtering | James J. Bonanno, Adam B. Collura, Ulrich Mayer, Brian R. Prasky, Chung-Lung K. Shum | 2015-09-15 |
| 9021240 | System and method for Controlling restarting of instruction fetching using speculative address computations | Khary J. Alexander, Brian R. Prasky, Robert J. Sonnelitter, III | 2015-04-28 |
| 8972665 | Cache set selective power up | Brian R. Prasky, Aaron Tsai | 2015-03-03 |
| 8874885 | Mitigating lookahead branch prediction latency by purposely stalling a branch instruction until a delayed branch prediction is received or a timeout occurs | James J. Bonanno, David S. Hutton, Brian R. Prasky | 2014-10-28 |
| 8443176 | Method, system, and computer program product for reducing cache memory pollution | Robert J. Sonnelitter, III, James J. Bonanno, David S. Hutton, Brian R. Prasky | 2013-05-14 |
| 7913068 | System and method for providing asynchronous dynamic millicode entry prediction | James J. Bonanno, Brian R. Prasky, John G. Rell, Jr., Chung-Lung K. Shum | 2011-03-22 |
| 7882338 | Method, system and computer program product for an implicit predicted return from a predicted subroutine | Khary J. Alexander, James J. Bonanno, Brian R. Prasky, Robert J. Sonnelitter, III, Charles F. Webb | 2011-02-01 |
| 7831775 | System and method for tracking changes in L1 data cache directory | Sheldon B. Levenstein | 2010-11-09 |
| 7822954 | Methods, systems, and computer program products for recovering from branch prediction latency | John W. Ward, III, Khary J. Alexander, James J. Bonanno, Brian R. Prasky, Robert J. Sonnelitter, III | 2010-10-26 |
| 7814374 | System and method for the capture and preservation of intermediate error state data | Douglas G. Balazich, Michael Billeci, Timothy J. Slegel | 2010-10-12 |
| 7805634 | Error accumulation register, error accumulation method, and error accumulation system | Douglas G. Balazich, Michael Billeci, Timothy J. Slegel | 2010-09-28 |
| 7752354 | Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processor | Miles Robert Dooley, Joaquin Hinojosa, Bruce Joseph Ronchetti | 2010-07-06 |
| 7603543 | Method, apparatus and program product for enhancing performance of an in-order processor with long stalls | Miles Robert Dooley, Scott Bruce Frommer, Hung Q. Le, Sheldon B. Levenstein | 2009-10-13 |
| 7571283 | Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch | Scott Bruce Frommer, Sheldon B. Levenstein, Bruce Joseph Ronchetti | 2009-08-04 |
| 7401186 | System and method for tracking changes in L1 data cache directory | Sheldon B. Levenstein | 2008-07-15 |
| 7380062 | Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch | Scott Bruce Frommer, Sheldon B. Levenstein, Bruce Joseph Ronchetti | 2008-05-27 |
| 7318127 | Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor | David A. Hrusecky, Sheldon B. Levenstein, Bruce Joseph Ronchetti | 2008-01-08 |
| 7284094 | Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class | David A. Hrusecky, Sheldon B. Levenstein, Bruce Joseph Ronchetti | 2007-10-16 |
| 7111196 | System and method for providing processor recovery in a multi-core system | Douglas G. Balazich, Michael Billeci, Timothy J. Slegel | 2006-09-19 |