Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10353707 | Efficient pointer load and format | Eyal Naor, Martin Recktenwald, Christian Zoellin | 2019-07-16 |
| 10169041 | Efficient pointer load and format | Eyal Naor, Martin Recktenwald, Christian Zoellin | 2019-01-01 |
| 9766896 | Optimizing grouping of instructions | Fadi Y. Busaba, Michael T. Huffer, David S. Hutton, Edward T. Malley, John G. Rell, Jr. +1 more | 2017-09-19 |
| 9710278 | Optimizing grouping of instructions | Fadi Y. Busaba, Michael T. Huffer, David S. Hutton, Edward T. Malley, John G. Rell, Jr. +1 more | 2017-07-18 |
| 9164761 | Obtaining data in a pipelined processor | Bruce C. Giamei, Chung-Lung K. Shum, Scott Barnett Swaney | 2015-10-20 |
| 8984261 | Store data forwarding with no memory model restrictions | Brian D. Barrick, Barry W. Krumm, James R. Mitchell, Bradley Nelson, Chung-Lung K. Shum +1 more | 2015-03-17 |
| 8972665 | Cache set selective power up | Brian R. Prasky, Anthony Saporito | 2015-03-03 |
| 8898426 | Target buffer address region tracking | James J. Bonanno, Brian R. Prasky | 2014-11-25 |
| 8898427 | Target buffer address region tracking | James J. Bonanno, Brian R. Prasky | 2014-11-25 |
| 8667258 | High performance cache translation look-aside buffer (TLB) lookups using multiple page size prediction | Brian R. Prasky, Gregory W. Alexander, James J. Bonanno, Joshua M. Weinberg | 2014-03-04 |
| 8645670 | Specialized store queue and buffer design for silent store implementation | Brian D. Barrick, Chung-Lung K. Shum | 2014-02-04 |
| 8627047 | Store data forwarding with no memory model restrictions | Barry W. Krumm, James R. Mitchell, Bradley Nelson, Brian D. Barrick, Chung-Lung K. Shum +1 more | 2014-01-07 |
| 8468306 | Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions | Barry W. Krumm, James R. Mitchell, Bradley Nelson, Brian D. Barrick, Chung-Lung K. Shum +1 more | 2013-06-18 |
| 8417890 | Managing cache coherency for self-modifying code in an out-of-order execution system | Christian Jacobi, Brian R. Prasky | 2013-04-09 |
| 8250336 | Method, system and computer program product for storing external device result data | Chung-Lung K. Shum, Brian D. Barrick, Thomas Koehler | 2012-08-21 |
| 8195881 | System, method and processor for accessing data after a translation lookaside buffer miss | Richard Esten Bohn, Ka Shan Choy, Chung-Lung K. Shum | 2012-06-05 |
| 8041894 | Method and system for a multi-level virtual/real cache system with synonym resolution | Barry W. Krumm, Christian Jacobi, Chung-Lung K. Shum, Hans-Werner Tast, Ching-Farn E. Wu | 2011-10-18 |
| 8015362 | Method and system for handling cache coherency for self-modifying code | Gregory W. Alexander, Christian Jacobi, Barry W. Krumm, Chung-Lung K. Shum | 2011-09-06 |
| 7987384 | Method, system, and computer program product for handling errors in a cache without processor core recovery | Christian Jacobi, Matthias Pflanz, Chung-Lung K. Shum, Hans-Werner Tast | 2011-07-26 |
| 7953932 | System and method for avoiding deadlocks when performing storage updates in a multi-processor environment | Chung-Lung K. Shum, Brian D. Barrick, Charles F. Webb | 2011-05-31 |
| 7890700 | Method, system, and computer program product for cross-invalidation handling in a multi-level private cache | Ka Shan Choy, Jennifer A. Navarro, Chung-Lung K. Shum | 2011-02-15 |
| 7870314 | Method and system for implementing store buffer allocation | Brian D. Barrick, Vimal M. Kapadia, Chung-Lung K. Shum | 2011-01-11 |
| 7039762 | Parallel cache interleave accesses with address-sliced directories | Jennifer A. Navarro, Chung-Lung K. Shum | 2006-05-02 |
| 7035986 | System and method for simultaneous access of the same line in cache storage | Mark A. Check, Jennifer A. Navarro, Chung-Lung K. Shum, Timothy J. Slegel | 2006-04-25 |
| 6990556 | System and method for simultaneous access of the same doubleword in cache storage | Mark A. Check | 2006-01-24 |